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Commit 527fad1b authored by Laxman Dewangan's avatar Laxman Dewangan Committed by Stephen Warren
Browse files

clk: tegra: initialise parent of uart clocks 



Initialise the parent of UARTs to PLLP and disabling clock by
default.

Signed-off-by: default avatarLaxman Dewangan <ldewangan@nvidia.com>
Acked-by: default avatarMike Turquette <mturquette@linaro.org>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent 8364f5d9

drivers/clk/tegra/clk-tegra20.c

+5 −2
Original line number Diff line number Diff line
@@ -1254,8 +1254,11 @@ static __initdata struct tegra_clk_init_table init_table[] = { 
	{csite, clk_max, 0, 1},

	{emc, clk_max, 0, 1},

	{cclk, clk_max, 0, 1},

	{uarta, pll_p, 0, 1},

	{uartd, pll_p, 0, 1},

	{uarta, pll_p, 0, 0},

	{uartb, pll_p, 0, 0},

	{uartc, pll_p, 0, 0},

	{uartd, pll_p, 0, 0},

	{uarte, pll_p, 0, 0},

	{usbd, clk_max, 12000000, 0},

	{usb2, clk_max, 12000000, 0},

	{usb3, clk_max, 12000000, 0},

drivers/clk/tegra/clk-tegra30.c

+5 −1
Original line number Diff line number Diff line
@@ -1877,7 +1877,11 @@ static struct tegra_cpu_car_ops tegra30_cpu_car_ops = { 
};



static __initdata struct tegra_clk_init_table init_table[] = {

	{uarta, pll_p, 408000000, 1},

	{uarta, pll_p, 408000000, 0},

	{uartb, pll_p, 408000000, 0},

	{uartc, pll_p, 408000000, 0},

	{uartd, pll_p, 408000000, 0},

	{uarte, pll_p, 408000000, 0},

	{pll_a, clk_max, 564480000, 1},

	{pll_a_out0, clk_max, 11289600, 1},

	{extern1, pll_a_out0, 0, 1},