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Commit 51b091e9 authored by Zhen Kong's avatar Zhen Kong
Browse files

crypto: msm: fix aes counter issue 



Counter Mask registers are not initialized for 128 bits of counter.
As the result, some test vector of aes(ctr) may fail.

Change-Id: Iccf83aff737d253fa8f8110684e40491bcee7035
Acked-by: default avatarChemin Hsieh <cheminh@qti.qualcomm.com>
Signed-off-by: default avatarZhen Kong <zkong@codeaurora.org>
parent 9e91c0c5

drivers/crypto/msm/qce50.c

+21 −2
Original line number Diff line number Diff line
@@ -1419,7 +1419,7 @@ static int _ce_setup_aead_direct(struct qce_device *pce_dev, 
		encr_cfg |= (1 << CRYPTO_ENCODE);

	QCE_WRITE_REG(encr_cfg, pce_dev->iobase + CRYPTO_ENCR_SEG_CFG_REG);



	/* we only support sha1-hmac and sha256-hmc at this point */

	/* we only support sha1-hmac and sha256-hmac at this point */

	_byte_stream_to_net_words(mackey32, q_req->authkey,

					q_req->authklen);

	for (i = 0; i < authk_size_in_word; i++)
@@ -1780,9 +1780,16 @@ static int _ce_setup_cipher_direct(struct qce_device *pce_dev, 
	/* write encr seg start */

	QCE_WRITE_REG((coffset & 0xffff),

			pce_dev->iobase + CRYPTO_ENCR_SEG_START_REG);

	/* write encr seg start */



	/* write encr counter mask */

	QCE_WRITE_REG(0xffffffff,

			pce_dev->iobase + CRYPTO_CNTR_MASK_REG);

	QCE_WRITE_REG(0xffffffff,

			pce_dev->iobase + CRYPTO_CNTR_MASK_REG0);

	QCE_WRITE_REG(0xffffffff,

			pce_dev->iobase + CRYPTO_CNTR_MASK_REG1);

	QCE_WRITE_REG(0xffffffff,

			pce_dev->iobase + CRYPTO_CNTR_MASK_REG2);



	/* write seg size  */

	QCE_WRITE_REG(totallen_in, pce_dev->iobase + CRYPTO_SEG_SIZE_REG);
@@ -3060,6 +3067,12 @@ static int _setup_cipher_aes_cmdlistptrs(struct qce_device *pdev, 
						&pcl_info->encr_seg_start);

	qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CNTR_MASK_REG,

				(uint32_t)0xffffffff, &pcl_info->encr_mask);

	qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CNTR_MASK_REG0,

				(uint32_t)0xffffffff, NULL);

	qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CNTR_MASK_REG1,

				(uint32_t)0xffffffff, NULL);

	qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CNTR_MASK_REG2,

				(uint32_t)0xffffffff, NULL);

	qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_SEG_CFG_REG, 0,

						&pcl_info->auth_seg_cfg);

	qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_ENCR_KEY0_REG, 0,
@@ -3674,6 +3687,12 @@ static int _setup_aead_ccm_cmdlistptrs(struct qce_device *pdev, 
						&pcl_info->encr_seg_start);

	qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CNTR_MASK_REG,

				(uint32_t)0xffffffff, &pcl_info->encr_mask);

	qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CNTR_MASK_REG0,

				(uint32_t)0xffffffff, NULL);

	qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CNTR_MASK_REG1,

				(uint32_t)0xffffffff, NULL);

	qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_CNTR_MASK_REG2,

				(uint32_t)0xffffffff, NULL);

	qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_SEG_CFG_REG,

					auth_cfg, &pcl_info->auth_seg_cfg);

	qce_add_cmd_element(pdev, &ce_vaddr, CRYPTO_AUTH_SEG_SIZE_REG, 0,

drivers/crypto/msm/qcryptohw_50.h

+4 −1
Original line number Diff line number Diff line 
/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.

/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -142,6 +142,9 @@ 
#define CRYPTO_CNTR2_IV2_REG			0x1A214

#define CRYPTO_CNTR3_IV3_REG			0x1A218



#define CRYPTO_CNTR_MASK_REG0			0x1A23C

#define CRYPTO_CNTR_MASK_REG1			0x1A238

#define CRYPTO_CNTR_MASK_REG2			0x1A234

#define CRYPTO_CNTR_MASK_REG			0x1A21C



#define CRYPTO_ENCR_CCM_INT_CNTR0_REG		0x1A220