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Commit 50de3d2a authored by Saravana Kannan's avatar Saravana Kannan
Browse files

ARM: dts: msm: Scale cache with CPUfreq using devfreq governor and device 



For SoCs with asynchronous cache:
- Add qcom,cache device to provide the clock and the list of usable
  frequencies to the devfreq clock driver. Also set the default governor
  for this device to "cpufreq".
- Add CPUfreq to cache freq mapping for the cache device.
- Enable the DEVFREQ_SIMPLE_DEV config for these targets.

Change-Id: I5bda30420e79935d8d660306dd25d45042a3945b
Signed-off-by: default avatarSaravana Kannan <skannan@codeaurora.org>
parent 108009e0

arch/arm/boot/dts/qcom/apq8084.dtsi

+41 −0
Original line number Diff line number Diff line
@@ -2535,6 +2535,34 @@ 
			< 2265600000  950000  726 >;

	};



	cache: qcom,cache {

		compatible = "devfreq-simple-dev";

		clock-names = "devfreq_clk";

		clocks = <&clock_krait clk_l2_clk>;

		governor = "cpufreq";

		freq-tbl-khz =

			<  300000 >,

			<  345600 >,

			<  422400 >,

			<  499200 >,

			<  576000 >,

			<  652800 >,

			<  729600 >,

			<  806400 >,

			<  883200 >,

			<  960000 >,

			< 1036800 >,

			< 1113600 >,

			< 1190400 >,

			< 1267200 >,

			< 1344000 >,

			< 1420800 >,

			< 1497600 >,

			< 1574400 >,

			< 1651200 >,

			< 1728000 >;

	};



	cpubw: qcom,cpubw {

		compatible = "qcom,cpubw";

		qcom,cpu-mem-ports = <1 512>;
@@ -2573,6 +2601,19 @@ 
				< 1728000 12145 >,

				< 2649600 16250 >;

		};

		cache-cpufreq {

			target-dev = <&cache>;

			cpu-to-dev-map =

				<  300000  300000 >,

				<  422400  422400 >,

				<  652800  499200 >,

				<  883200  576000 >,

				<  960000  960000 >,

				< 1497600 1036800 >,

				< 1574400 1574400 >,

				< 1728000 1651200 >,

				< 2649600 1728000 >;

		};

	};



	qcom,msm-cpufreq {

arch/arm/boot/dts/qcom/fsm9900.dtsi

+41 −0
Original line number Diff line number Diff line
@@ -663,6 +663,33 @@ 
				"tsens_tz_sensor5", "tsens_tz_sensor6";

	};



	cache: qcom,cache {

		compatible = "devfreq-simple-dev";

		clock-names = "devfreq_clk";

		clocks = <&clock_krait clk_l2_clk>;

		governor = "cpufreq";

		freq-tbl-khz =

			<  300000 >,

			<  345600 >,

			<  422400 >,

			<  499200 >,

			<  576000 >,

			<  652800 >,

			<  729600 >,

			<  806400 >,

			<  883200 >,

			<  960000 >,

			< 1036800 >,

			< 1113600 >,

			< 1190400 >,

			< 1267200 >,

			< 1344000 >,

			< 1420800 >,

			< 1497600 >,

			< 1574400 >,

			< 1651200 >;

	};



	cpubw: qcom,cpubw {

		compatible = "qcom,cpubw";

		qcom,cpu-mem-ports = <1 512>, <2 512>;
@@ -684,6 +711,20 @@ 
				< 1190400 3509 >,

				< 2265600 6103 >;

		};

		cache-cpufreq {

			target-dev = <&cache>;

			cpu-to-dev-map =

				<  300000  300000 >,

				<  422400  422400 >,

				<  576000  576000 >,

				<  729600  729600 >,

				<  883200  883200 >,

				< 1036800 1036800 >,

				< 1190400 1190400 >,

				< 1344000 1344000 >,

				< 1497600 1497600 >,

				< 2265600 1651200 >;

		};

	};



	qcom,msm-cpufreq {

arch/arm/boot/dts/qcom/msm8974.dtsi

+43 −0
Original line number Diff line number Diff line
@@ -1433,6 +1433,34 @@ 
			< 2265600000  925000 691 >;

	};



	cache: qcom,cache {

		compatible = "devfreq-simple-dev";

		clock-names = "devfreq_clk";

		clocks = <&clock_krait clk_l2_clk>;

		governor = "cpufreq";

		freq-tbl-khz =

			<  300000 >,

			<  345600 >,

			<  422400 >,

			<  499200 >,

			<  576000 >,

			<  652800 >,

			<  729600 >,

			<  806400 >,

			<  883200 >,

			<  960000 >,

			< 1036800 >,

			< 1113600 >,

			< 1190400 >,

			< 1267200 >,

			< 1344000 >,

			< 1420800 >,

			< 1497600 >,

			< 1574400 >,

			< 1651200 >,

			< 1728000 >;

	};



	cpubw: qcom,cpubw {

		compatible = "qcom,cpubw";

		qcom,cpu-mem-ports = <1 512>, <2 512>;
@@ -1468,6 +1496,21 @@ 
				< 1728000 6103 >,

				< 2457600 7102 >;

		};

		cache-cpufreq {

			target-dev = <&cache>;

			cpu-to-dev-map =

				<  300000  300000 >,

				<  422400  422400 >,

				<  652800  499200 >,

				<  883200  576000 >,

				<  960000  960000 >,

				< 1190400 1036800 >,

				< 1267200 1267200 >,

				< 1497600 1497600 >,

				< 1574400 1574400 >,

				< 1728000 1651200 >,

				< 2457600 1728000 >;

		};

	};



	qcom,msm-cpufreq {

arch/arm/mach-msm/Kconfig

+3 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ config ARCH_MSM8974 
	select MSM_GPIOMUX

	select PM_DEVFREQ

	select MSM_DEVFREQ_CPUBW

	select DEVFREQ_SIMPLE_DEV

	select MSM_PIL

	select MSM_SPM_V2

	select MSM_L2_SPM
@@ -67,6 +68,7 @@ config ARCH_APQ8084 
	select KRAIT_REGULATOR

	select PM_DEVFREQ

	select MSM_DEVFREQ_CPUBW

	select DEVFREQ_SIMPLE_DEV

	select MSM_PIL

	select ENABLE_VMALLOC_SAVINGS

	select MSM_ULTRASOUND
@@ -120,6 +122,7 @@ config ARCH_FSM9900 
	select MSM_GPIOMUX

	select PM_DEVFREQ

	select MSM_DEVFREQ_CPUBW

	select DEVFREQ_SIMPLE_DEV

	select MSM_PIL

	select REGULATOR

	select ARM_HAS_SG_CHAIN

arch/arm64/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -142,6 +142,7 @@ config ARCH_MSM 
	select CPU_FREQ_MSM

	select PM_DEVFREQ

	select MSM_DEVFREQ_CPUBW

	select DEVFREQ_SIMPLE_DEV

	help

	  This enables support for the ARMv8 based Qualcomm chipsets.