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Commit 50dcb4ac authored by Lucille Sylvester's avatar Lucille Sylvester Committed by Suman Tatiraju
Browse files

msm: kgsl: Disable SP/TP power collapse 



Simplify the control path for the SP/TP power collapse feature.
Make the sysfs variable "sptp_pc" and write 1 to enable power collapse,
0 to disable.  Explicitly list the feature for adreno cores where it
is enabled.

Change-Id: I9a47b7a62013d74944df1f478240ae66c2db742f
Signed-off-by: default avatarLucille Sylvester <lsylvest@codeaurora.org>
parent d81481d4

drivers/gpu/msm/adreno-gpulist.h

+1 −1
Original line number Diff line number Diff line
@@ -179,7 +179,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.minor = 0,

		.patchid = ANY_ID,

		.features = ADRENO_USES_OCMEM  | ADRENO_WARM_START |

			ADRENO_USE_BOOTSTRAP,

			ADRENO_USE_BOOTSTRAP | ADRENO_SPTP_PC,

		.pm4fw_name = "a420_pm4.fw",

		.pfpfw_name = "a420_pfp.fw",

		.gpudev = &adreno_a4xx_gpudev,

drivers/gpu/msm/adreno.c

+59 −18
Original line number Diff line number Diff line
@@ -1968,6 +1968,10 @@ static int _adreno_start(struct adreno_device *adreno_dev) 


	adreno_perfcounter_start(adreno_dev);



	/* Enable h/w power collapse feature */

	if (gpudev->enable_pc)

		gpudev->enable_pc(adreno_dev);



	status = adreno_ringbuffer_cold_start(adreno_dev);

	if (status)

		goto error_irq_off;
@@ -2520,6 +2524,59 @@ static ssize_t _wake_timeout_show(struct device *dev, 
	return snprintf(buf, PAGE_SIZE, "%u\n", _wake_timeout);

}



/**

 * _sptp_pc_store() - Enable or disable SP/TP power collapse

 * @dev: device ptr

 * @attr: Device attribute

 * @buf: value to write

 * @count: size of the value to write

 *

 */

static ssize_t _sptp_pc_store(struct device *dev,

				struct device_attribute *attr,

				const char *buf, size_t count)

{

	struct adreno_device *adreno_dev = _get_adreno_dev(dev);

	struct kgsl_device *device = kgsl_device_from_dev(dev);

	struct adreno_gpudev *gpudev;

	int ret, t = 0;



	if ((adreno_dev == NULL) || (device == NULL))

		return -ENODEV;



	gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	ret = kgsl_sysfs_store(buf, &t);

	if (ret < 0)

		return ret;



	kgsl_mutex_lock(&device->mutex, &device->mutex_owner);



	kgsl_pwrctrl_change_state(device, KGSL_STATE_SUSPEND);

	if (t)

		set_bit(ADRENO_SPTP_PC_CTRL, &adreno_dev->pwrctrl_flag);

	else

		clear_bit(ADRENO_SPTP_PC_CTRL, &adreno_dev->pwrctrl_flag);

	kgsl_pwrctrl_change_state(device, KGSL_STATE_SLUMBER);



	kgsl_mutex_unlock(&device->mutex, &device->mutex_owner);

	return count;

}



/**

 * _sptp_pc_show() -  Show whether SP/TP power collapse is enabled

 * @dev: device ptr

 * @attr: Device attribute

 * @buf: value read

 */

static ssize_t _sptp_pc_show(struct device *dev,

					struct device_attribute *attr,

					char *buf)

{

	struct adreno_device *adreno_dev = _get_adreno_dev(dev);

	return snprintf(buf, PAGE_SIZE, "%u\n", test_bit(ADRENO_SPTP_PC_CTRL,

					&adreno_dev->pwrctrl_flag));

}



#define ADRENO_DEVICE_ATTR(name) \

	DEVICE_ATTR(name, 0644,	_ ## name ## _show, _ ## name ## _store);
@@ -2531,6 +2588,7 @@ static ADRENO_DEVICE_ATTR(ft_hang_intr_status); 


static DEVICE_INT_ATTR(wake_nice, 0644, _wake_nice);

static ADRENO_DEVICE_ATTR(wake_timeout);

static ADRENO_DEVICE_ATTR(sptp_pc);



static const struct device_attribute *_attr_list[] = {

	&dev_attr_ft_policy,
@@ -2540,6 +2598,7 @@ static const struct device_attribute *_attr_list[] = { 
	&dev_attr_ft_hang_intr_status,

	&dev_attr_wake_nice.attr,

	&dev_attr_wake_timeout,

	&dev_attr_sptp_pc,

	NULL,

};
@@ -3302,22 +3361,6 @@ static unsigned int adreno_gpuid(struct kgsl_device *device, 
	return (0x0003 << 16) | ADRENO_GPUREV(adreno_dev);

}



static void adreno_enable_pc(struct kgsl_device *device)

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	struct adreno_gpudev *gpudev  = ADRENO_GPU_DEVICE(adreno_dev);

	if (gpudev->enable_pc)

		gpudev->enable_pc(adreno_dev);

}



static void adreno_disable_pc(struct kgsl_device *device)

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	struct adreno_gpudev *gpudev  = ADRENO_GPU_DEVICE(adreno_dev);

	if (gpudev->disable_pc)

		gpudev->disable_pc(adreno_dev);

}



static void adreno_regulator_enable(struct kgsl_device *device)

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
@@ -3374,8 +3417,6 @@ static const struct kgsl_functable adreno_functable = { 
	.setproperty_compat = adreno_setproperty_compat,

	.drawctxt_sched = adreno_drawctxt_sched,

	.resume = adreno_dispatcher_start,

	.enable_pc = adreno_enable_pc,

	.disable_pc = adreno_disable_pc,

	.regulator_enable = adreno_regulator_enable,

	.is_hw_collapsible = adreno_is_hw_collapsible,

	.regulator_disable = adreno_regulator_disable,

drivers/gpu/msm/adreno.h

+5 −1
Original line number Diff line number Diff line
@@ -74,6 +74,8 @@ 
#define ADRENO_USE_BOOTSTRAP  BIT(3)

/* The microcode for the code supports the IOMMU sync lock functionality */

#define ADRENO_HAS_IOMMU_SYNC_LOCK BIT(4)

/* The core supports SP/TP hw controlled power collapse */

#define ADRENO_SPTP_PC BIT(5)



/* Flags to control command packet settings */

#define KGSL_CMD_FLAGS_NONE             0
@@ -130,6 +132,8 @@ enum adreno_gpurev { 
#define ADRENO_TIMEOUT_FAULT BIT(2)

#define ADRENO_IOMMU_PAGE_FAULT BIT(3)



#define ADRENO_SPTP_PC_CTRL BIT(0)



/*

 * Maximum size of the dispatcher ringbuffer - the actual inflight size will be

 * smaller then this but this size will allow for a larger range of inflight
@@ -266,6 +270,7 @@ struct adreno_device { 
	unsigned int starved_ram_lo;

	atomic_t halt;

	struct dentry *ctx_d_debugfs;

	unsigned long pwrctrl_flag;

};



/**
@@ -624,7 +629,6 @@ struct adreno_gpudev { 
	void (*soft_reset)(struct adreno_device *device);

	bool (*is_sptp_idle)(struct adreno_device *);

	void (*enable_pc)(struct adreno_device *);

	void (*disable_pc)(struct adreno_device *);

	void (*regulator_enable)(struct adreno_device *);

	void (*regulator_disable)(struct adreno_device *);

};

drivers/gpu/msm/adreno_a3xx.c

+0 −5
Original line number Diff line number Diff line
@@ -1064,15 +1064,10 @@ int a3xx_perfcounter_enable(struct adreno_device *adreno_dev, 
	}

	reg = &(counters->groups[group].regs[counter]);



	if (adreno_is_a4xx(adreno_dev))

		gpudev->disable_pc(adreno_dev);

	/* Select the desired perfcounter */

	kgsl_regwrite(&adreno_dev->dev, reg->select, countable);

	counters->groups[group].regs[counter].value = 0;



	if (adreno_is_a4xx(adreno_dev))

		gpudev->enable_pc(adreno_dev);



	return 0;

}

drivers/gpu/msm/adreno_a4xx.c

+5 −35
Original line number Diff line number Diff line
@@ -18,8 +18,6 @@ 
#include "adreno_cp_parser.h"

#include "adreno_trace.h"



#define SP_TP_PWR_COLLAPSE_MASK 0x6

#define SP_TP_PWR_ON_MASK BIT(0)

#define SP_TP_PWR_ON BIT(20)



/*
@@ -316,7 +314,7 @@ static bool a4xx_is_sptp_idle(struct adreno_device *adreno_dev) 
{

	unsigned int reg;

	struct kgsl_device *device = &adreno_dev->dev;

	if (adreno_is_a420(adreno_dev))

	if (!ADRENO_FEATURE(adreno_dev, ADRENO_SPTP_PC))

		return true;



	/* If SP/TP pc isn't enabled, don't worry about power */
@@ -340,7 +338,7 @@ static void a4xx_regulator_enable(struct adreno_device *adreno_dev) 
{

	unsigned int reg;

	struct kgsl_device *device = &adreno_dev->dev;

	if (adreno_is_a420(adreno_dev))

	if (!ADRENO_FEATURE(adreno_dev, ADRENO_SPTP_PC))

		return;



	/* Set the default register values; set SW_COLLAPSE to 0 */
@@ -363,7 +361,7 @@ static void a4xx_regulator_enable(struct adreno_device *adreno_dev) 
static void a4xx_regulator_disable(struct adreno_device *adreno_dev)

{

	struct kgsl_device *device = &adreno_dev->dev;

	if (adreno_is_a420(adreno_dev))

	if (!ADRENO_FEATURE(adreno_dev, ADRENO_SPTP_PC))

		return;



	/* Set the default register values; set SW_COLLAPSE to 1 */
@@ -377,41 +375,15 @@ static void a4xx_regulator_disable(struct adreno_device *adreno_dev) 
 */

static void a4xx_enable_pc(struct adreno_device *adreno_dev)

{

	unsigned int reg;

	struct kgsl_device *device = &adreno_dev->dev;

	if (adreno_is_a420(adreno_dev))

	if (!ADRENO_FEATURE(adreno_dev, ADRENO_SPTP_PC) ||

		!test_bit(ADRENO_SPTP_PC_CTRL, &adreno_dev->pwrctrl_flag))

		return;



	kgsl_regread(device, A4XX_RBBM_POWER_CNTL_IP, &reg);

	reg = (reg & ~SP_TP_PWR_COLLAPSE_MASK);

	kgsl_regwrite(device, A4XX_RBBM_POWER_CNTL_IP, reg);

	kgsl_regwrite(device, A4XX_CP_POWER_COLLAPSE_CNTL, 0x00400010);

	trace_adreno_sp_tp((unsigned long) __builtin_return_address(0));

};



/*

 * a4xx_disable_pc() - Disable the SP/TP block power collapse

 * @adreno_dev: The adreno device pointer

 */

static void a4xx_disable_pc(struct adreno_device *adreno_dev)

{

	unsigned int reg;

	struct kgsl_device *device = &adreno_dev->dev;

	if (adreno_is_a420(adreno_dev))

		return;



	/* remove hw control and use the sw override */

	kgsl_regread(device, A4XX_RBBM_POWER_CNTL_IP, &reg);

	reg = (reg & ~SP_TP_PWR_COLLAPSE_MASK) | 0x4;

	kgsl_regwrite(device, A4XX_RBBM_POWER_CNTL_IP, reg);



	/* turn the SP/TP on & restore it */

	a4xx_regulator_enable(adreno_dev);

	kgsl_regwrite(device, A4XX_HLSQ_STATE_RESTORE_TRIGGER, 0x1);

	trace_adreno_sp_tp((unsigned long) __builtin_return_address(0));

}





/*

 * a4xx_enable_hwcg() - Program the clock control registers

 * @device: The adreno device pointer
@@ -631,7 +603,6 @@ static void a4xx_start(struct adreno_device *adreno_dev) 
	}



	a4xx_enable_hwcg(device);

	a4xx_enable_pc(adreno_dev);

	/*

	 * For A420 set RBBM_CLOCK_DELAY_HLSQ.CGC_HLSQ_TP_EARLY_CYC >= 2

	 * due to timing issue with HLSQ_TP_CLK_EN
@@ -1444,7 +1415,6 @@ struct adreno_gpudev adreno_a4xx_gpudev = { 
	.snapshot = a4xx_snapshot,

	.is_sptp_idle = a4xx_is_sptp_idle,

	.enable_pc = a4xx_enable_pc,

	.disable_pc = a4xx_disable_pc,

	.regulator_enable = a4xx_regulator_enable,

	.regulator_disable = a4xx_regulator_disable,

};