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Commit 50d07d85 authored by Ujwal Patel's avatar Ujwal Patel
Browse files

msm: mdss: Use single flush method for 8084 split display 



Split display use-cases have two independent control paths. MDSS before
8084 requires both control paths to program their own flush registers
which can lead to race conditions. Starting 8084, MDSS HW can achieve
same flush but with only single register write and eliminating race
conditions.

Change-Id: I62e5d61decb6f20cbd9bec542e035471b84b2c0a
Signed-off-by: default avatarUjwal Patel <ujwalp@codeaurora.org>
parent bd02dc6d

drivers/video/msm/mdss/mdss_mdp_ctl.c

+12 −4
Original line number Diff line number Diff line
@@ -1011,8 +1011,11 @@ static void mdss_mdp_ctl_split_display_enable(int enable, 
	MDSS_MDP_REG_WRITE(MDSS_MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTRL, upper);

	MDSS_MDP_REG_WRITE(MDSS_MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTRL, lower);

	MDSS_MDP_REG_WRITE(MDSS_MDP_REG_SPLIT_DISPLAY_EN, enable);

}



	if (main_ctl->mdata->mdp_rev >= MDSS_MDP_HW_REV_103)

		MDSS_MDP_REG_WRITE(MMSS_MDP_MDP_SSPP_SPARE_0,

			enable ? 0x1 : 0x0);

}



int mdss_mdp_ctl_destroy(struct mdss_mdp_ctl *ctl)

{
@@ -1802,15 +1805,20 @@ int mdss_mdp_display_commit(struct mdss_mdp_ctl *ctl, void *arg) 


	/* postprocessing setup, including dspp */

	mdss_mdp_pp_setup_locked(ctl);



	if (sctl && ctl->mdata->mdp_rev >= MDSS_MDP_HW_REV_103) {

		ctl->flush_bits |= sctl->flush_bits;

		sctl->flush_bits = 0;

	}



	mdss_mdp_ctl_write(ctl, MDSS_MDP_REG_CTL_FLUSH, ctl->flush_bits);

	if (sctl) {

	if (sctl && sctl->flush_bits) {

		mdss_mdp_ctl_write(sctl, MDSS_MDP_REG_CTL_FLUSH,

			sctl->flush_bits);

		sctl->flush_bits = 0;

	}

	wmb();

	ctl->flush_bits = 0;

	if (sctl)

		sctl->flush_bits = 0;



	if (ctl->display_fnc)

		ret = ctl->display_fnc(ctl, arg); /* kickoff */

drivers/video/msm/mdss/mdss_mdp_hwio.h

+1 −0
Original line number Diff line number Diff line
@@ -44,6 +44,7 @@ 
#define MDSS_MDP_REG_HIST_INTR_EN			0x0011C

#define MDSS_MDP_REG_HIST_INTR_STATUS			0x00120

#define MDSS_MDP_REG_HIST_INTR_CLEAR			0x00124

#define MMSS_MDP_MDP_SSPP_SPARE_0			0x00128



#define MDSS_MDP_REG_VIDEO_INTF_UNDERFLOW_CTL		0x003E0

#define MDSS_MDP_REG_SPLIT_DISPLAY_EN			0x003F4