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Commit 4f8968c5 authored by Stepan Moskovchenko's avatar Stepan Moskovchenko
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ARM: dts: msm: Add L1 / L2 cache dump nodes for 8992



Add the nodes needed to define the dumping regions for the
A53/A57 L1 instruction and data caches, as well as the A57
L2 cache. Dumping the contents of the L2 cache on the A53
cluster is not currently supported.

Change-Id: Iabdd90f99e67baa5ca53eb9dfa81c953d110d516
Signed-off-by: default avatarStepan Moskovchenko <stepanm@codeaurora.org>
parent 18c43109
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