Merge "scsi: ufs-msm: rename all entities from "msm" to "qcom"" (4ececa58) · Commits · e / devices / android_kernel_sony_msm8994

drivers/scsi/ufs/ufs-msm-phy-qmp-20nm.c

+55 −53

Original line number	Diff line number	Diff line
		@@ -25,13 +25,14 @@
		#include "ufs-msm-phy.h"
		#include "ufs-msm-phy-qmp-20nm.h"

		#define UFS_PHY_NAME "ufs_msm_phy_qmp_20nm"
		#define UFS_PHY_NAME "ufs_phy_qmp_20nm"

		static int ufs_msm_phy_qmp_20nm_phy_calibrate(struct ufs_msm_phy *ufs_msm_phy)
		static
		int ufs_qcom_phy_qmp_20nm_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy)
		{
		struct ufs_msm_phy_calibration tbl_A, tbl_B;
		struct ufs_qcom_phy_calibration tbl_A, tbl_B;
		int tbl_size_A, tbl_size_B;
		int rate = UFS_MSM_LIMIT_HS_RATE;
		int rate = UFS_QCOM_LIMIT_HS_RATE;
		int err;

		tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A);
		@@ -40,52 +41,55 @@ static int ufs_msm_phy_qmp_20nm_phy_calibrate(struct ufs_msm_phy *ufs_msm_phy)
		tbl_size_B = ARRAY_SIZE(phy_cal_table_rate_B);
		tbl_B = phy_cal_table_rate_B;

		err = ufs_msm_phy_calibrate(ufs_msm_phy, tbl_A, tbl_size_A,
		err = ufs_qcom_phy_calibrate(ufs_qcom_phy, tbl_A, tbl_size_A,
		tbl_B, tbl_size_B, rate);

		if (err)
		dev_err(ufs_msm_phy->dev, "%s: ufs_msm_phy_calibrate() failed %d\n",
		dev_err(ufs_qcom_phy->dev, "%s: ufs_qcom_phy_calibrate() failed %d\n",
		__func__, err);

		return err;
		}

		static
		void ufs_msm_phy_qmp_20nm_advertise_quirks(struct ufs_msm_phy *phy_common)
		void ufs_qcom_phy_qmp_20nm_advertise_quirks(struct ufs_qcom_phy *phy_common)
		{
		phy_common->quirks =
		MSM_UFS_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE;
		UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE;
		}

		static int ufs_msm_phy_qmp_20nm_init(struct phy *generic_phy)
		static int ufs_qcom_phy_qmp_20nm_init(struct phy *generic_phy)
		{
		struct ufs_msm_phy_qmp_20nm *phy = phy_get_drvdata(generic_phy);
		struct ufs_msm_phy *phy_common = &phy->common_cfg;
		struct ufs_qcom_phy_qmp_20nm *phy = phy_get_drvdata(generic_phy);
		struct ufs_qcom_phy *phy_common = &phy->common_cfg;
		int err = 0;

		err = ufs_msm_phy_init_clks(generic_phy, phy_common);
		err = ufs_qcom_phy_init_clks(generic_phy, phy_common);
		if (err) {
		dev_err(phy_common->dev, "%s: ufs_msm_phy_init_clks() failed %d\n",
		dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_clks() failed %d\n",
		__func__, err);
		goto out;
		}

		err = ufs_msm_phy_init_vregulators(generic_phy, phy_common);
		err = ufs_qcom_phy_init_vregulators(generic_phy, phy_common);
		if (err) {
		dev_err(phy_common->dev, "%s: ufs_msm_phy_init_vregulators() failed %d\n",
		dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_vregulators() failed %d\n",
		__func__, err);
		goto out;
		}

		ufs_msm_phy_qmp_20nm_advertise_quirks(phy_common);
		ufs_qcom_phy_qmp_20nm_advertise_quirks(phy_common);

		out:
		return err;
		}

		static
		void ufs_msm_phy_qmp_20nm_power_control(struct ufs_msm_phy *phy, bool val)
		void ufs_qcom_phy_qmp_20nm_power_control(struct ufs_qcom_phy *phy, bool val)
		{
		bool hibern8_exit_after_pwr_collapse = phy->quirks &
		UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE;

		if (val) {
		writel_relaxed(0x1, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
		/*
		@@ -94,8 +98,7 @@ void ufs_msm_phy_qmp_20nm_power_control(struct ufs_msm_phy *phy, bool val)
		*/
		mb();

		if (phy->quirks &
		MSM_UFS_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE) {
		if (hibern8_exit_after_pwr_collapse) {
		/*
		* Give atleast 1us delay after restoring PHY analog
		* power.
		@@ -112,8 +115,7 @@ void ufs_msm_phy_qmp_20nm_power_control(struct ufs_msm_phy *phy, bool val)
		mb();
		}
		} else {
		if (phy->quirks &
		MSM_UFS_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE) {
		if (hibern8_exit_after_pwr_collapse) {
		writel_relaxed(0x0A, phy->mmio +
		QSERDES_COM_SYSCLK_EN_SEL_TXBAND);
		writel_relaxed(0x02, phy->mmio +
		@@ -135,14 +137,14 @@ void ufs_msm_phy_qmp_20nm_power_control(struct ufs_msm_phy *phy, bool val)
		}

		static
		void ufs_msm_phy_qmp_20nm_set_tx_lane_enable(struct ufs_msm_phy *phy, u32 val)
		void ufs_qcom_phy_qmp_20nm_set_tx_lane_enable(struct ufs_qcom_phy *phy, u32 val)
		{
		writel_relaxed(val & UFS_PHY_TX_LANE_ENABLE_MASK,
		phy->mmio + UFS_PHY_TX_LANE_ENABLE);
		mb();
		}

		static inline void ufs_msm_phy_qmp_20nm_start_serdes(struct ufs_msm_phy *phy)
		static inline void ufs_qcom_phy_qmp_20nm_start_serdes(struct ufs_qcom_phy *phy)
		{
		u32 tmp;

		@@ -153,7 +155,7 @@ static inline void ufs_msm_phy_qmp_20nm_start_serdes(struct ufs_msm_phy *phy)
		mb();
		}

		static int ufs_msm_phy_qmp_20nm_is_pcs_ready(struct ufs_msm_phy *phy_common)
		static int ufs_qcom_phy_qmp_20nm_is_pcs_ready(struct ufs_qcom_phy *phy_common)
		{
		int err = 0;
		u32 val;
		@@ -166,27 +168,27 @@ static int ufs_msm_phy_qmp_20nm_is_pcs_ready(struct ufs_msm_phy *phy_common)
		return err;
		}

		struct phy_ops ufs_msm_phy_qmp_20nm_phy_ops = {
		.init = ufs_msm_phy_qmp_20nm_init,
		.exit = ufs_msm_phy_exit,
		.power_on = ufs_msm_phy_power_on,
		.power_off = ufs_msm_phy_power_off,
		struct phy_ops ufs_qcom_phy_qmp_20nm_phy_ops = {
		.init = ufs_qcom_phy_qmp_20nm_init,
		.exit = ufs_qcom_phy_exit,
		.power_on = ufs_qcom_phy_power_on,
		.power_off = ufs_qcom_phy_power_off,
		.owner = THIS_MODULE,
		};

		struct ufs_msm_phy_specific_ops phy_20nm_ops = {
		.calibrate_phy = ufs_msm_phy_qmp_20nm_phy_calibrate,
		.start_serdes = ufs_msm_phy_qmp_20nm_start_serdes,
		.is_physical_coding_sublayer_ready = ufs_msm_phy_qmp_20nm_is_pcs_ready,
		.set_tx_lane_enable = ufs_msm_phy_qmp_20nm_set_tx_lane_enable,
		.power_control = ufs_msm_phy_qmp_20nm_power_control,
		struct ufs_qcom_phy_specific_ops phy_20nm_ops = {
		.calibrate_phy = ufs_qcom_phy_qmp_20nm_phy_calibrate,
		.start_serdes = ufs_qcom_phy_qmp_20nm_start_serdes,
		.is_physical_coding_sublayer_ready = ufs_qcom_phy_qmp_20nm_is_pcs_ready,
		.set_tx_lane_enable = ufs_qcom_phy_qmp_20nm_set_tx_lane_enable,
		.power_control = ufs_qcom_phy_qmp_20nm_power_control,
		};

		static int ufs_msm_phy_qmp_20nm_probe(struct platform_device *pdev)
		static int ufs_qcom_phy_qmp_20nm_probe(struct platform_device *pdev)
		{
		struct device *dev = &pdev->dev;
		struct phy *generic_phy;
		struct ufs_msm_phy_qmp_20nm *phy;
		struct ufs_qcom_phy_qmp_20nm *phy;
		int err = 0;

		phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
		@@ -196,11 +198,11 @@ static int ufs_msm_phy_qmp_20nm_probe(struct platform_device *pdev)
		goto out;
		}

		generic_phy = ufs_msm_phy_generic_probe(pdev, &phy->common_cfg,
		&ufs_msm_phy_qmp_20nm_phy_ops, &phy_20nm_ops);
		generic_phy = ufs_qcom_phy_generic_probe(pdev, &phy->common_cfg,
		&ufs_qcom_phy_qmp_20nm_phy_ops, &phy_20nm_ops);

		if (!generic_phy) {
		dev_err(dev, "%s: ufs_msm_phy_generic_probe() failed\n",
		dev_err(dev, "%s: ufs_qcom_phy_generic_probe() failed\n",
		__func__);
		err = -EIO;
		goto out;
		@@ -215,38 +217,38 @@ out:
		return err;
		}

		static int ufs_msm_phy_qmp_20nm_remove(struct platform_device *pdev)
		static int ufs_qcom_phy_qmp_20nm_remove(struct platform_device *pdev)
		{
		struct device *dev = &pdev->dev;
		struct phy *generic_phy = to_phy(dev);
		struct ufs_msm_phy *ufs_msm_phy = get_ufs_msm_phy(generic_phy);
		struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
		int err = 0;

		err = ufs_msm_phy_remove(generic_phy, ufs_msm_phy);
		err = ufs_qcom_phy_remove(generic_phy, ufs_qcom_phy);
		if (err)
		dev_err(dev, "%s: ufs_msm_phy_remove failed = %d\n",
		dev_err(dev, "%s: ufs_qcom_phy_remove failed = %d\n",
		__func__, err);

		return err;
		}

		static const struct of_device_id ufs_msm_phy_qmp_20nm_of_match[] = {
		static const struct of_device_id ufs_qcom_phy_qmp_20nm_of_match[] = {
		{.compatible = "qcom,ufs-msm-phy-qmp-20nm"},
		{},
		};
		MODULE_DEVICE_TABLE(of, ufs_msm_phy_qmp_20nm_of_match);
		MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qmp_20nm_of_match);

		static struct platform_driver ufs_msm_phy_qmp_20nm_driver = {
		.probe = ufs_msm_phy_qmp_20nm_probe,
		.remove = ufs_msm_phy_qmp_20nm_remove,
		static struct platform_driver ufs_qcom_phy_qmp_20nm_driver = {
		.probe = ufs_qcom_phy_qmp_20nm_probe,
		.remove = ufs_qcom_phy_qmp_20nm_remove,
		.driver = {
		.of_match_table = ufs_msm_phy_qmp_20nm_of_match,
		.name = "ufs_msm_phy_qmp_20nm",
		.of_match_table = ufs_qcom_phy_qmp_20nm_of_match,
		.name = "ufs_qcom_phy_qmp_20nm",
		.owner = THIS_MODULE,
		},
		};

		module_platform_driver(ufs_msm_phy_qmp_20nm_driver);
		module_platform_driver(ufs_qcom_phy_qmp_20nm_driver);

		MODULE_DESCRIPTION("Universal Flash Storage (UFS) MSM PHY QMP 20nm");
		MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QMP 20nm");
		MODULE_LICENSE("GPL v2");

drivers/scsi/ufs/ufs-msm-phy-qmp-20nm.h

+89 −89

Original line number	Diff line number	Diff line
		@@ -12,12 +12,12 @@
		*
		*/

		#ifndef UFS_MSM_PHY_QMP_20NM_H_
		#define UFS_MSM_PHY_QMP_20NM_H_
		#ifndef UFS_QCOM_PHY_QMP_20NM_H_
		#define UFS_QCOM_PHY_QMP_20NM_H_

		#include "ufs-msm-phy.h"

		/* MSM UFS PHY control registers */
		/* QCOM UFS PHY control registers */

		#define COM_OFF(x) (0x000 + x)
		#define PHY_OFF(x) (0xC00 + x)
		@@ -119,98 +119,98 @@
		* This structure represents the 20nm specific phy.
		* common_cfg MUST remain the first field in this structure
		* in case extra fields are added. This way, when calling
		* get_ufs_msm_phy() of generic phy, we can extract the
		* common phy structure (struct ufs_msm_phy) out of it
		* get_ufs_qcom_phy() of generic phy, we can extract the
		* common phy structure (struct ufs_qcom_phy) out of it
		* regardless of the relevant specific phy.
		*/
		struct ufs_msm_phy_qmp_20nm {
		struct ufs_msm_phy common_cfg;
		struct ufs_qcom_phy_qmp_20nm {
		struct ufs_qcom_phy common_cfg;
		};

		static struct ufs_msm_phy_calibration phy_cal_table_rate_A[] = {
		UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_VCOTAIL_EN, 0xe1),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CRCTRL, 0xcc),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL_TXBAND, 0x08),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CLKEPDIV, 0x03),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RXTXEPCLK_EN, 0x10),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x82),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START2, 0x03),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1, 0x80),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2, 0x80),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3, 0x40),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0xff),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x19),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP3, 0x00),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP_EN, 0x03),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x90),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL2, 0x03),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL1(0), 0xf2),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(0), 0x0c),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(0), 0x12),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL1(1), 0xf2),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(1), 0x0c),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(1), 0x12),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB(0), 0xff),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB(0), 0xff),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB(0), 0xff),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB(0), 0x00),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB(1), 0xff),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB(1), 0xff),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB(1), 0xff),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB(1), 0x00),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETI, 0x3f),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETP, 0x1b),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETP, 0x0f),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETI, 0x01),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_EMP_POST1_LVL(0), 0x2F),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_DRV_LVL(0), 0x20),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_EMP_POST1_LVL(1), 0x2F),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_DRV_LVL(1), 0x20),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(0), 0x68),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(1), 0x68),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(1), 0xdc),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(0), 0xdc),
		static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = {
		UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_VCOTAIL_EN, 0xe1),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CRCTRL, 0xcc),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL_TXBAND, 0x08),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CLKEPDIV, 0x03),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RXTXEPCLK_EN, 0x10),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x82),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START2, 0x03),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1, 0x80),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2, 0x80),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3, 0x40),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0xff),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x19),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP3, 0x00),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP_EN, 0x03),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x90),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL2, 0x03),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL1(0), 0xf2),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(0), 0x0c),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(0), 0x12),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL1(1), 0xf2),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(1), 0x0c),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(1), 0x12),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB(0), 0xff),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB(0), 0xff),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB(0), 0xff),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB(0), 0x00),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB(1), 0xff),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB(1), 0xff),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB(1), 0xff),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB(1), 0x00),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETI, 0x3f),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETP, 0x1b),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETP, 0x0f),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETI, 0x01),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_EMP_POST1_LVL(0), 0x2F),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_DRV_LVL(0), 0x20),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_EMP_POST1_LVL(1), 0x2F),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_DRV_LVL(1), 0x20),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(0), 0x68),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(1), 0x68),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(1), 0xdc),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(0), 0xdc),
		};

		static struct ufs_msm_phy_calibration phy_cal_table_rate_B[] = {
		UFS_MSM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CRCTRL, 0xcc),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL_TXBAND, 0x08),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CLKEPDIV, 0x03),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RXTXEPCLK_EN, 0x10),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x98),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START2, 0x03),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1, 0x80),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2, 0x80),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3, 0x40),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0x65),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x1e),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP3, 0x00),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP_EN, 0x03),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x90),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL1(0), 0xf2),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(0), 0x0c),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(0), 0x12),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL1(1), 0xf2),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(1), 0x0c),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(1), 0x12),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB(0), 0xff),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB(0), 0xff),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB(0), 0xff),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB(0), 0x00),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB(1), 0xff),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB(1), 0xff),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB(1), 0xff),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB(1), 0x00),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETI, 0x3f),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETP, 0x1b),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETP, 0x0f),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETI, 0x01),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(0), 0x68),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(1), 0x68),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(1), 0xdc),
		UFS_MSM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(0), 0xdc),
		static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = {
		UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CRCTRL, 0xcc),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL_TXBAND, 0x08),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CLKEPDIV, 0x03),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RXTXEPCLK_EN, 0x10),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START1, 0x98),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START2, 0x03),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1, 0x80),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2, 0x80),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3, 0x40),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP1, 0x65),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP2, 0x1e),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP3, 0x00),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLLLOCK_CMP_EN, 0x03),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x90),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL1(0), 0xf2),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(0), 0x0c),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(0), 0x12),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL1(1), 0xf2),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_HALF(1), 0x0c),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_CDR_CONTROL_QUARTER(1), 0x12),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB(0), 0xff),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB(0), 0xff),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB(0), 0xff),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB(0), 0x00),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB(1), 0xff),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB(1), 0xff),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB(1), 0xff),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB(1), 0x00),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETI, 0x3f),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETP, 0x1b),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CP_SETP, 0x0f),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IP_SETI, 0x01),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(0), 0x68),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE(1), 0x68),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(1), 0xdc),
		UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2(0), 0xdc),
		};

		#endif

drivers/scsi/ufs/ufs-msm-phy-qmp-28nm.c

+67 −66

File changed.

Preview size limit exceeded, changes collapsed.

drivers/scsi/ufs/ufs-msm-phy-qmp-28nm.h

+329 −326

File changed.

Preview size limit exceeded, changes collapsed.

drivers/scsi/ufs/ufs-msm-phy.c

+137 −133

File changed.

Preview size limit exceeded, changes collapsed.