Commit 4eb75b03 authored Feb 03, 2015 by Karthik Parsha

soc: cpu_pwr_ctl: Update LDO init values based on characterization



On some parts, when the LDO voltage is configured and the LDO is
is setup to be used, the LDO output voltage goes back up to the
same value as the upstream PMIC voltage. This causes a power drain
even after switching to LDO. LDO_CGF1 controls the Phase Transient
characteristics of the LDO. Increasing the value programmed to
LDO_CFG1 allows the LDO to stabilize at the given voltage by changing
phase transient characteristics of the LDO. The higher value would
allow the LDO output to stabilize at the set value.
Update A53 and A57 LDO_CFG1 value based on updated LDO300 hardware
characterization data.

Change-Id: I95bb356f63432699b65873075bb46d4e002723c1
Signed-off-by: Karthik Parsha <kparsha@codeaurora.org>

parent c96b0bd7

drivers/soc/qcom/cpu_pwr_ctl.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -331,7 +331,7 @@ int msm8994_cpu_ldo_config(unsigned int cpu)
		val = (val & 0xffffff00) \| 0xc2;
		writel_relaxed(val, ldo_bhs_reg_base + APC_LDO_CFG1);
		val = readl_relaxed(ldo_bhs_reg_base + APC_LDO_CFG1);
		val = (val & 0xffff00ff) \| (0x98 << 8);
		val = (val & 0xffff00ff) \| (0xf8 << 8);
		writel_relaxed(val, ldo_bhs_reg_base + APC_LDO_CFG1);
		val = readl_relaxed(ldo_bhs_reg_base + APC_LDO_CFG2);
		val = (val & 0xffffff00) \| 0x60;