ARM: exynos4: convert to CONFIG_MULTI_IRQ_HANDLER (4e44d2cb) · Commits · e / devices / android_kernel_sony_msm8994

arch/arm/Kconfig

+1 −0

Original line number	Original line	Diff line number	Diff line
	@@ -854,6 +854,7 @@ config ARCH_EXYNOS
	select HAVE_S3C2410_I2C if I2C		select HAVE_S3C2410_I2C if I2C
	select HAVE_S3C2410_WATCHDOG if WATCHDOG		select HAVE_S3C2410_WATCHDOG if WATCHDOG
	select NEED_MACH_MEMORY_H		select NEED_MACH_MEMORY_H
			select MULTI_IRQ_HANDLER
	help		help
	Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)		Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)

arch/arm/mach-exynos/cpu.c

+2 −2

Original line number	Original line	Diff line number	Diff line
	@@ -15,6 +15,7 @@
	#include <asm/mach/irq.h>		#include <asm/mach/irq.h>

	#include <asm/proc-fns.h>		#include <asm/proc-fns.h>
			#include <asm/exception.h>
	#include <asm/hardware/cache-l2x0.h>		#include <asm/hardware/cache-l2x0.h>
	#include <asm/hardware/gic.h>		#include <asm/hardware/gic.h>

	@@ -33,8 +34,6 @@
	#include <mach/regs-irq.h>		#include <mach/regs-irq.h>
	#include <mach/regs-pmu.h>		#include <mach/regs-pmu.h>

	unsigned int gic_bank_offset __read_mostly;

	extern int combiner_init(unsigned int combiner_nr, void __iomem *base,		extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
	unsigned int irq_start);		unsigned int irq_start);
	extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);		extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
	@@ -210,6 +209,7 @@ void __init exynos4_init_clocks(int xtal)
	void __init exynos4_init_irq(void)		void __init exynos4_init_irq(void)
	{		{
	int irq;		int irq;
			unsigned int bank_offset;

	gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;		gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;

arch/arm/mach-exynos/include/mach/entry-macro.S

+0 −75

Original line number	Original line	Diff line number	Diff line
	@@ -9,83 +9,8 @@
	* warranty of any kind, whether express or implied.		* warranty of any kind, whether express or implied.
	*/		*/

	#include <mach/hardware.h>
	#include <mach/map.h>
	#include <asm/hardware/gic.h>

	.macro disable_fiq		.macro disable_fiq
	.endm		.endm

	.macro get_irqnr_preamble, base, tmp
	mov \tmp, #0

	mrc p15, 0, \base, c0, c0, 5
	and \base, \base, #3
	cmp \base, #0
	beq 1f

	ldr \tmp, =gic_bank_offset
	ldr \tmp, [\tmp]
	cmp \base, #1
	beq 1f

	cmp \base, #2
	addeq \tmp, \tmp, \tmp
	addne \tmp, \tmp, \tmp, LSL #1

	1: ldr \base, =gic_cpu_base_addr
	ldr \base, [\base]
	add \base, \base, \tmp
	.endm

	.macro arch_ret_to_user, tmp1, tmp2		.macro arch_ret_to_user, tmp1, tmp2
	.endm		.endm

	/*
	* The interrupt numbering scheme is defined in the
	* interrupt controller spec. To wit:
	*
	* Interrupts 0-15 are IPI
	* 16-28 are reserved
	* 29-31 are local. We allow 30 to be used for the watchdog.
	* 32-1020 are global
	* 1021-1022 are reserved
	* 1023 is "spurious" (no interrupt)
	*
	* For now, we ignore all local interrupts so only return an interrupt if it's
	* between 30 and 1020. The test_for_ipi routine below will pick up on IPIs.
	*
	* A simple read from the controller will tell us the number of the highest
	* priority enabled interrupt. We then just need to check whether it is in the
	* valid range for an IRQ (30-1020 inclusive).
	*/

	.macro get_irqnr_and_base, irqnr, irqstat, base, tmp

	ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */

	ldr \tmp, =1021

	bic \irqnr, \irqstat, #0x1c00

	cmp \irqnr, #15
	cmpcc \irqnr, \irqnr
	cmpne \irqnr, \tmp
	cmpcs \irqnr, \irqnr
	addne \irqnr, \irqnr, #32

	.endm

	/* We assume that irqstat (the raw value of the IRQ acknowledge
	* register) is preserved from the macro above.
	* If there is an IPI, we immediately signal end of interrupt on the
	* controller, since this requires the original irqstat value which
	* we won't easily be able to recreate later.
	*/

	.macro test_for_ipi, irqnr, irqstat, base, tmp
	bic \irqnr, \irqstat, #0x1c00
	cmp \irqnr, #16
	strcc \irqstat, [\base, #GIC_CPU_EOI]
	cmpcs \irqnr, \irqnr
	.endm

arch/arm/mach-exynos/mach-armlex4210.c

+2 −0

Original line number	Original line	Diff line number	Diff line
	@@ -16,6 +16,7 @@
	#include <linux/smsc911x.h>		#include <linux/smsc911x.h>

	#include <asm/mach/arch.h>		#include <asm/mach/arch.h>
			#include <asm/hardware/gic.h>
	#include <asm/mach-types.h>		#include <asm/mach-types.h>

	#include <plat/cpu.h>		#include <plat/cpu.h>
	@@ -210,6 +211,7 @@ MACHINE_START(ARMLEX4210, "ARMLEX4210")
	.atag_offset = 0x100,		.atag_offset = 0x100,
	.init_irq = exynos4_init_irq,		.init_irq = exynos4_init_irq,
	.map_io = armlex4210_map_io,		.map_io = armlex4210_map_io,
			.handle_irq = gic_handle_irq,
	.init_machine = armlex4210_machine_init,		.init_machine = armlex4210_machine_init,
	.timer = &exynos4_timer,		.timer = &exynos4_timer,
	MACHINE_END		MACHINE_END

arch/arm/mach-exynos/mach-nuri.c

+2 −0

Original line number	Original line	Diff line number	Diff line
	@@ -32,6 +32,7 @@
	#include <media/v4l2-mediabus.h>		#include <media/v4l2-mediabus.h>

	#include <asm/mach/arch.h>		#include <asm/mach/arch.h>
			#include <asm/hardware/gic.h>
	#include <asm/mach-types.h>		#include <asm/mach-types.h>

	#include <plat/adc.h>		#include <plat/adc.h>
	@@ -1333,6 +1334,7 @@ MACHINE_START(NURI, "NURI")
	.atag_offset = 0x100,		.atag_offset = 0x100,
	.init_irq = exynos4_init_irq,		.init_irq = exynos4_init_irq,
	.map_io = nuri_map_io,		.map_io = nuri_map_io,
			.handle_irq = gic_handle_irq,
	.init_machine = nuri_machine_init,		.init_machine = nuri_machine_init,
	.timer = &exynos4_timer,		.timer = &exynos4_timer,
	.reserve = &nuri_reserve,		.reserve = &nuri_reserve,