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Commit 4ac39f69 authored by Vikram Mulukutla's avatar Vikram Mulukutla
Browse files

ARM: dts: msm: Add clock controller devices for the MSM8974 



Add the RPM, GCC, MMSS and LPASS clock controller devices
to the device tree for the 8974. This will allow the clock
drivers to probe these devices and register the necessary
clock tables.

Change-Id: Ic8d2da8a2d84ce2b66d35c5f63b93559b7dea36f
Signed-off-by: default avatarVikram Mulukutla <markivx@codeaurora.org>
parent 76ccdc74

arch/arm/boot/dts/msm8974-v2.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -47,6 +47,14 @@ 
		compatible = "qcom,msm-imem";

		reg = <0xfe805000 0x1000>; /* Address and size of IMEM */

	};



	qcom,gcc@fc400000 {

		compatible = "qcom,gcc-8974v2";

	};



	qcom,mmsscc@fd8c0000 {

		compatible = "qcom,mmsscc-8974v2";

	};

};



/* GPU overrides */

arch/arm/boot/dts/msm8974.dtsi

+38 −0
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ 
 */



#include "skeleton.dtsi"

#include <dt-bindings/clock/msm-clocks-8974.h>



/ {

	model = "Qualcomm MSM 8974";
@@ -134,6 +135,43 @@ 
		qcom,direct-connect-irqs = <8>;

	};



	clock_rpm: qcom,rpmcc@fc4000000 {

		compatible = "qcom,rpmcc-8974";

		reg = <0xfc400000 0x4000>;

		reg-names = "cc_base";

		#clock-cells = <1>;

	};



	clock_gcc: qcom,gcc@fc400000 {

		compatible = "qcom,gcc-8974";

		reg = <0xfc400000 0x4000>;

		reg-names = "cc_base";

		vdd_dig-supply = <&pm8841_s2_corner>;

		#clock-cells = <1>;

	};



	clock_mmss: qcom,mmsscc@fd8c0000 {

		compatible = "qcom,mmsscc-8974";

		reg = <0xfd8c0000 0x40000>;

		reg-names = "cc_base";

		vdd_dig-supply = <&pm8841_s2_corner>;

		#clock-cells = <1>;

	};



	clock_lpass: qcom,lpasscc@fe000000 {

		compatible = "qcom,lpasscc-8974";

		reg = <0xfe000000 0x40000>;

		reg-names = "cc_base";

		vdd_dig-supply = <&pm8841_s2_corner>;

		#clock-cells = <1>;

	};



	clock_debug: qcom,cc-debug@fc401880 {

		compatible = "qcom,cc-debug-8974";

		reg = <0xfc401880 0x4>;

		#clock-cells = <1>;

	};



	wcd9xxx_intc: wcd9xxx-irq {

		compatible = "qcom,wcd9xxx-irq";

		interrupt-controller;

arch/arm/boot/dts/msm8974pro-pma8084.dtsi

+13 −0
Original line number Diff line number Diff line
@@ -106,6 +106,19 @@ 
		hfpll-analog-supply = <&pma8084_l12_ao>;

	};



	qcom,gcc@fc400000 {

		compatible = "qcom,gcc-8974pro-ac";

		vdd_dig-supply = <&pma8084_s2_corner>;

	};



	qcom,mmsscc@fd8c0000 {

		vdd_dig-supply = <&pma8084_s2_corner>;

	};



	qcom,lpasscc@fe000000 {

		vdd_dig-supply = <&pma8084_s2_corner>;

	};



	qcom,ssusb@f9200000 {

		/delete-property/ vbus_dwc3-supply;

		/delete-property/ qcom,misc-ref;

arch/arm/boot/dts/msm8974pro.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -1566,6 +1566,14 @@ 
			    "lpaif_tert_mode_muxsel",

			    "lpaif_quat_mode_muxsel";

	};



	qcom,gcc@fc400000 {

		compatible = "qcom,gcc-8974pro";

	};



	qcom,mmsscc@fd8c0000 {

		compatible = "qcom,mmsscc-8974pro";

	};

};



/* GPU overrides */

include/dt-bindings/clock/msm-clocks-8974.h

0 → 100644
+287 −0
Original line number Diff line number Diff line 
/* Copyright (c) 2013, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef __MSM_CLOCKS_8974_H

#define __MSM_CLOCKS_8974_H



#define clk_acpu_aux_clk 0x871939dd

#define clk_analog_postdiv_clk_8974 0x8ef10676

#define clk_axi_clk_src 0x6617efab

#define clk_bimc_a_clk 0x4b25668a

#define clk_bimc_acpu_a_clk 0x4446311b

#define clk_bimc_clk 0x4b80bf00

#define clk_bimc_msmbus_a_clk 0x71d1a499

#define clk_bimc_msmbus_clk 0xd212feea

#define clk_byte_clk_src_8974 0x405e7995

#define clk_byte_mux_8974 0x82a3afc5

#define clk_camss_cci_cci_ahb_clk 0x12aec62d

#define clk_camss_cci_cci_clk 0xc9a1bf11

#define clk_camss_csi0_ahb_clk 0x6e29c972

#define clk_camss_csi0_clk 0x30862ddb

#define clk_camss_csi0phy_clk 0x2cecfb84

#define clk_camss_csi0pix_clk 0x6946f77b

#define clk_camss_csi0rdi_clk 0x83645ef5

#define clk_camss_csi1_ahb_clk 0xccc15f06

#define clk_camss_csi1_clk 0xb150f052

#define clk_camss_csi1phy_clk 0xb989f06d

#define clk_camss_csi1pix_clk 0x58d19bf3

#define clk_camss_csi1rdi_clk 0x4d2f3352

#define clk_camss_csi2_ahb_clk 0x92d02d75

#define clk_camss_csi2_clk 0x74fc92e8

#define clk_camss_csi2phy_clk 0xda05d9d8

#define clk_camss_csi2pix_clk 0xf8ed0731

#define clk_camss_csi2rdi_clk 0xdc1b2081

#define clk_camss_csi3_ahb_clk 0xee5e459c

#define clk_camss_csi3_clk 0x39488fdd

#define clk_camss_csi3phy_clk 0x8b6063b9

#define clk_camss_csi3pix_clk 0xd82bd467

#define clk_camss_csi3rdi_clk 0xb6750046

#define clk_camss_csi_vfe0_clk 0x3023937a

#define clk_camss_csi_vfe1_clk 0xe66fa522

#define clk_camss_gp0_clk 0xcee7e51d

#define clk_camss_gp1_clk 0x41f1c2e3

#define clk_camss_ispif_ahb_clk 0x9a212c6d

#define clk_camss_jpeg_jpeg0_clk 0xa1f09a89

#define clk_camss_jpeg_jpeg1_clk 0x32952078

#define clk_camss_jpeg_jpeg2_clk 0xd3a2ff99

#define clk_camss_jpeg_jpeg_ahb_clk 0x2b877145

#define clk_camss_jpeg_jpeg_axi_clk 0x07eeae7b

#define clk_camss_jpeg_jpeg_ocmemnoc_clk 0x92ff5e81

#define clk_camss_mclk0_clk 0xcf0c61e0

#define clk_camss_mclk1_clk 0xd1410ed4

#define clk_camss_mclk2_clk 0x851286f2

#define clk_camss_mclk3_clk 0x4db11c45

#define clk_camss_micro_ahb_clk 0x33a23277

#define clk_camss_phy0_csi0phytimer_clk 0x02248c8b

#define clk_camss_phy1_csi1phytimer_clk 0x690fe05b

#define clk_camss_phy2_csi2phytimer_clk 0x93daa279

#define clk_camss_top_ahb_clk 0x8f8b2d33

#define clk_camss_vfe_cpp_ahb_clk 0xea097d83

#define clk_camss_vfe_cpp_clk 0x3ca47975

#define clk_camss_vfe_vfe0_clk 0x373027a2

#define clk_camss_vfe_vfe1_clk 0xb8d03898

#define clk_camss_vfe_vfe_ahb_clk 0xbd885885

#define clk_camss_vfe_vfe_axi_clk 0x8412c7db

#define clk_camss_vfe_vfe_ocmemnoc_clk 0x03b9a73b

#define clk_cci_clk_src 0x822f3d97

#define clk_ce1_clk_src 0x8e8c7e03

#define clk_ce2_clk_src 0x34793cec

#define clk_cnoc_a_clk 0xd8fe2ccc

#define clk_cnoc_clk 0xd5ccb7f4

#define clk_cnoc_msmbus_a_clk 0x67442955

#define clk_cnoc_msmbus_clk 0x62228b5d

#define clk_csi0_clk_src 0x227e65bc

#define clk_csi0phytimer_clk_src 0xc8a309be

#define clk_csi1_clk_src 0x6a2a6c36

#define clk_csi1phytimer_clk_src 0x7c0fe23a

#define clk_csi2_clk_src 0x4113589f

#define clk_csi2phytimer_clk_src 0x62ffea9c

#define clk_csi3_clk_src 0xfd934012

#define clk_cxo_a2 0x994c579f

#define clk_cxo_a2_a_pin 0xc24f6753

#define clk_cxo_a_clk_src 0x3dba80d6

#define clk_cxo_d1_a_pin 0xa853a1a6

#define clk_cxo_dwc3_clk 0xf79c19f6

#define clk_cxo_ehci_host_clk 0x8098f53b

#define clk_cxo_gcc 0xdcd75806

#define clk_cxo_lpm_clk 0x94adbf3d

#define clk_cxo_mmss 0xe716f06d

#define clk_cxo_otg_clk 0x4eec0bb9

#define clk_cxo_pil_lpass_clk 0xe17f0ff6

#define clk_cxo_pil_mss_clk 0xdaceb23b

#define clk_cxo_pil_pronto_clk 0xdcc396d2

#define clk_cxo_wlan_clk 0x7d92783f

#define clk_diff_clk 0xb21cb5b5

#define clk_div_clk1 0xaa1157a6

#define clk_div_clk2 0xd454019f

#define clk_dsi_vco_clk_8974 0xda0caaea

#define clk_gcc_bam_dma_ahb_clk 0xaacf5929

#define clk_gcc_blsp1_ahb_clk 0x8caa5b4f

#define clk_gcc_blsp1_qup1_i2c_apps_clk 0xc303fae9

#define clk_gcc_blsp1_qup1_spi_apps_clk 0x759a76b0

#define clk_gcc_blsp1_qup2_i2c_apps_clk 0x1076f220

#define clk_gcc_blsp1_qup2_spi_apps_clk 0x3e77d48f

#define clk_gcc_blsp1_qup3_i2c_apps_clk 0x9e25ac82

#define clk_gcc_blsp1_qup3_spi_apps_clk 0xfb978880

#define clk_gcc_blsp1_qup4_i2c_apps_clk 0xd7f40f6f

#define clk_gcc_blsp1_qup4_spi_apps_clk 0x80f8722f

#define clk_gcc_blsp1_qup5_i2c_apps_clk 0xacae5604

#define clk_gcc_blsp1_qup5_spi_apps_clk 0xbf3e15d7

#define clk_gcc_blsp1_qup6_i2c_apps_clk 0x5c6ad820

#define clk_gcc_blsp1_qup6_spi_apps_clk 0x780d9f85

#define clk_gcc_blsp1_uart1_apps_clk 0xc7c62f90

#define clk_gcc_blsp1_uart2_apps_clk 0xf8a61c96

#define clk_gcc_blsp1_uart3_apps_clk 0xc3298bd7

#define clk_gcc_blsp1_uart4_apps_clk 0x26be16c0

#define clk_gcc_blsp1_uart5_apps_clk 0x28a6bc74

#define clk_gcc_blsp1_uart6_apps_clk 0x28fd3466

#define clk_gcc_blsp2_ahb_clk 0x8f283c1d

#define clk_gcc_blsp2_qup1_i2c_apps_clk 0x9ace11dd

#define clk_gcc_blsp2_qup1_spi_apps_clk 0xa32604cc

#define clk_gcc_blsp2_qup2_i2c_apps_clk 0x1bf9a57e

#define clk_gcc_blsp2_qup2_spi_apps_clk 0xbf54ca6d

#define clk_gcc_blsp2_qup3_i2c_apps_clk 0x336d4170

#define clk_gcc_blsp2_qup3_spi_apps_clk 0xc68509d6

#define clk_gcc_blsp2_qup4_i2c_apps_clk 0xbd22539d

#define clk_gcc_blsp2_qup4_spi_apps_clk 0x01a72b93

#define clk_gcc_blsp2_qup5_i2c_apps_clk 0xe2b2ce1d

#define clk_gcc_blsp2_qup5_spi_apps_clk 0xf40999cd

#define clk_gcc_blsp2_qup6_i2c_apps_clk 0x894bcea4

#define clk_gcc_blsp2_qup6_spi_apps_clk 0xfe1bd34a

#define clk_gcc_blsp2_uart1_apps_clk 0x8c3512ff

#define clk_gcc_blsp2_uart2_apps_clk 0x1e1965a3

#define clk_gcc_blsp2_uart3_apps_clk 0x382415ab

#define clk_gcc_blsp2_uart4_apps_clk 0x87a44b42

#define clk_gcc_blsp2_uart5_apps_clk 0x5cd30649

#define clk_gcc_blsp2_uart6_apps_clk 0x8feee5ab

#define clk_gcc_boot_rom_ahb_clk 0xde2adeb1

#define clk_gcc_ce1_ahb_clk 0x7408a16f

#define clk_gcc_ce1_axi_clk 0xafb3e588

#define clk_gcc_ce1_clk 0xc1c80572

#define clk_gcc_ce2_ahb_clk 0xc9c433b9

#define clk_gcc_ce2_axi_clk 0x724b2b8f

#define clk_gcc_ce2_clk 0xaf52701c

#define clk_gcc_debug_mux 0x8121ac15

#define clk_gcc_gp1_clk 0x057f7b69

#define clk_gcc_gp2_clk 0x9bf83ffd

#define clk_gcc_gp3_clk 0xec6539ee

#define clk_gcc_lpass_q6_axi_clk 0xa9612654

#define clk_gcc_mmss_noc_cfg_ahb_clk 0xb41a9d99

#define clk_gcc_mss_cfg_ahb_clk 0x111cde81

#define clk_gcc_mss_q6_bimc_axi_clk 0x67544d62

#define clk_gcc_ocmem_noc_cfg_ahb_clk 0x01d72ea1

#define clk_gcc_pdm2_clk 0x99d55711

#define clk_gcc_pdm_ahb_clk 0x365664f6

#define clk_gcc_prng_ahb_clk 0x397e7eaa

#define clk_gcc_sdcc1_ahb_clk 0x691e0caa

#define clk_gcc_sdcc1_apps_clk 0x9ad6fb96

#define clk_gcc_sdcc1_cdccal_ff_clk 0x5513de45

#define clk_gcc_sdcc1_cdccal_sleep_clk 0x5d79b68d

#define clk_gcc_sdcc2_ahb_clk 0x23d5727f

#define clk_gcc_sdcc2_apps_clk 0x861b20ac

#define clk_gcc_sdcc3_ahb_clk 0x565b2c03

#define clk_gcc_sdcc3_apps_clk 0x0b27aeac

#define clk_gcc_sdcc4_ahb_clk 0x64f3e6a8

#define clk_gcc_sdcc4_apps_clk 0xbf7c4dc8

#define clk_gcc_sys_noc_usb3_axi_clk 0x94d26800

#define clk_gcc_tsif_ahb_clk 0x88d2822c

#define clk_gcc_tsif_ref_clk 0x8f1ed2c2

#define clk_gcc_usb2a_phy_sleep_clk 0x6caa736f

#define clk_gcc_usb2b_phy_sleep_clk 0x8e94e9c8

#define clk_gcc_usb30_master_clk 0xb3b4e2cb

#define clk_gcc_usb30_mock_utmi_clk 0xa800b65a

#define clk_gcc_usb30_sleep_clk 0xd0b65c92

#define clk_gcc_usb_hs_ahb_clk 0x72ce8032

#define clk_gcc_usb_hs_system_clk 0xa11972e5

#define clk_gcc_usb_hsic_ahb_clk 0x3ec2631a

#define clk_gcc_usb_hsic_clk 0x8de18b0e

#define clk_gcc_usb_hsic_io_cal_clk 0xbc21f776

#define clk_gcc_usb_hsic_system_clk 0x145e9366

#define clk_gp1_clk_src 0xad85b97a

#define clk_gpll0_ao_clk_src 0x6b2fb034

#define clk_gpll0_clk_src 0x5933b69f

#define clk_gpll4_clk_src 0x10525d57

#define clk_hfpll0_clk 0xbf1858b6

#define clk_hfpll0_div_clk 0x27c60c55

#define clk_hfpll1_clk 0xfe5bec02

#define clk_hfpll1_div_clk 0xd895ec77

#define clk_hfpll2_clk 0xadc552ea

#define clk_hfpll2_div_clk 0x58846715

#define clk_hfpll3_clk 0xbe3bfe69

#define clk_hfpll3_div_clk 0x3a26e0ad

#define clk_hfpll_l2_clk 0xa31404e2

#define clk_hfpll_l2_div_clk 0xa9400306

#define clk_hfpll_src_clk 0xa6e8d53c

#define clk_indirect_path_div2_clk_8974 0x28ca6e0d

#define clk_kpss_debug_pri_mux 0x75345e43

#define clk_krait0_clk 0x79f36ab2

#define clk_krait0_pri_mux_clk 0xe6221f05

#define clk_krait0_sec_mux_clk 0xed9f6692

#define clk_krait1_clk 0x5d5c6818

#define clk_krait1_pri_mux_clk 0x51c1e512

#define clk_krait1_sec_mux_clk 0xcf209039

#define clk_krait2_clk 0xfb13e34f

#define clk_krait2_pri_mux_clk 0x6d925267

#define clk_krait2_sec_mux_clk 0xbdb892b3

#define clk_krait3_clk 0x3a0c5991

#define clk_krait3_pri_mux_clk 0x8cb8e774

#define clk_krait3_sec_mux_clk 0x19ad080d

#define clk_l2_clk 0x8d1f685e

#define clk_l2_pri_mux_clk 0xf42964b7

#define clk_l2_sec_mux_clk 0x0ee505f1

#define clk_mclk0_clk_src 0x266b3853

#define clk_mclk1_clk_src 0xa73cad0c

#define clk_mclk2_clk_src 0x42545468

#define clk_mdp_clk_src 0x6dc1f8f1

#define clk_mdss_ahb_clk 0x684ccb41

#define clk_mdss_axi_clk 0xcc07d687

#define clk_mdss_byte0_clk 0xf5a03f64

#define clk_mdss_byte1_clk 0xb8c7067d

#define clk_mdss_edpaux_clk 0x922d79ee

#define clk_mdss_edplink_clk 0xa04e7500

#define clk_mdss_edppixel_clk 0xb0011f51

#define clk_mdss_esc0_clk 0x28cafbe6

#define clk_mdss_esc1_clk 0xc22c6883

#define clk_mdss_extpclk_clk 0xfa5aadb0

#define clk_mdss_hdmi_ahb_clk 0x01cef516

#define clk_mdss_hdmi_clk 0x097a6de9

#define clk_mdss_mdp_clk 0x618336ac

#define clk_mdss_mdp_lut_clk 0x81a28e41

#define clk_mdss_pclk0_clk 0x3487234a

#define clk_mdss_pclk1_clk 0xd5804246

#define clk_mdss_vsync_clk 0x42a022d3

#define clk_mmss_debug_mux 0xe646ffda

#define clk_mmss_gp0_clk_src 0x081d3661

#define clk_mmss_gp1_clk_src 0xc620f96d

#define clk_mmss_misc_ahb_clk 0xea30b0e7

#define clk_mmss_mmssnoc_axi_clk 0x63753a4b

#define clk_mmss_s0_axi_clk 0xcbd7b001

#define clk_mmssnoc_ahb 0x66fd8dc9

#define clk_mmssnoc_ahb_clk 0xccd4bd4c

#define clk_ocmemcx_ocmemnoc_clk 0x37acd041

#define clk_ocmemgx_a_clk 0x310204ad

#define clk_ocmemgx_clk 0xc91618fb

#define clk_ocmemgx_core_clk 0xaad7dbe5

#define clk_ocmemgx_msmbus_a_clk 0x66dd774f

#define clk_ocmemgx_msmbus_clk 0x3968c738

#define clk_ocmemnoc_clk 0xd1660ae3

#define clk_oxili_gfx3d_clk 0x40c75e70

#define clk_oxili_gfx3d_clk_src 0xe0405056

#define clk_oxilicx_ahb_clk 0xcc8b032c

#define clk_oxilicx_axi_clk 0x9c3d82b4

#define clk_pixel_clk_src_8974 0xe7dea689

#define clk_pnoc_a_clk 0x2808c12b

#define clk_pnoc_clk 0x4325d220

#define clk_pnoc_keepalive_a_clk 0xf8f91f0b

#define clk_pnoc_msmbus_a_clk 0x8c9b4e93

#define clk_pnoc_msmbus_clk 0x38b95c77

#define clk_pnoc_pm_clk 0xd6f7dfb9

#define clk_pnoc_sps_clk 0xd482ecc7

#define clk_q6ss_ahb_lfabif_clk 0x26b5b318

#define clk_q6ss_ahbm_clk 0x9d1c4532

#define clk_q6ss_xo_clk 0x0c89ac5d

#define clk_qdss_a_clk 0xdd121669

#define clk_qdss_clk 0x1492202a

#define clk_rpm_debug_mux 0x25cd1f3a

#define clk_snoc_a_clk 0x8fcef2af

#define clk_snoc_clk 0x2c341aa0

#define clk_snoc_msmbus_a_clk 0x5d4683bd

#define clk_snoc_msmbus_clk 0xe6900bb6

#define clk_vcodec0_clk_src 0xbc193019

#define clk_venus0_ahb_clk 0x6694087d

#define clk_venus0_axi_clk 0x34fecbbe

#define clk_venus0_ocmemnoc_clk 0x590416b8

#define clk_venus0_vcodec0_clk 0xaf0dbde4

#define clk_vfe0_clk_src 0xa0c2bd8f

#define clk_vfe1_clk_src 0x4e357366



#endif