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Commit 43b54ae7 authored by William Clark's avatar William Clark
Browse files

ARM: dts: msm: Add multi-core crypto support for 8994 



Add support for multiple crypto instances, new apis are added
to provide information on the crypto instances available.

Change-Id: Ibedd61a72e12f86a7a5de15e9d274ceb4dfeada6
Signed-off-by: default avatarWilliam Clark <wclark@codeaurora.org>
parent b5c1c0ed

arch/arm/boot/dts/qcom/msm8994-cdp.dtsi

+13 −1
Original line number Diff line number Diff line
@@ -658,7 +658,19 @@ 
	status = "ok";

};



&qcom_crypto {

&qcom_crypto1fde {

	status = "okay";

};



&qcom_crypto2fde {

	status = "okay";

};



&qcom_crypto1pfe {

	status = "okay";

};



&qcom_crypto2pfe {

	status = "okay";

};

arch/arm/boot/dts/qcom/msm8994-fluid.dtsi

+13 −1
Original line number Diff line number Diff line
@@ -557,7 +557,19 @@ 
	status = "ok";

};



&qcom_crypto {

&qcom_crypto1fde {

	status = "okay";

};



&qcom_crypto2fde {

	status = "okay";

};



&qcom_crypto1pfe {

	status = "okay";

};



&qcom_crypto2pfe {

	status = "okay";

};

arch/arm/boot/dts/qcom/msm8994-mtp.dtsi

+13 −1
Original line number Diff line number Diff line
@@ -638,7 +638,19 @@ 
	status = "ok";

};



&qcom_crypto {

&qcom_crypto1fde {

	status = "okay";

};



&qcom_crypto2fde {

	status = "okay";

};



&qcom_crypto1pfe {

	status = "okay";

};



&qcom_crypto2pfe {

	status = "okay";

};

arch/arm/boot/dts/qcom/msm8994.dtsi

+85 −5
Original line number Diff line number Diff line
@@ -2445,14 +2445,14 @@ 
		reg = <0xfe87f720 0x1000>;

	};



	qcom_crypto: qcrypto@fd440000 {

	qcom_crypto1fde: qcrypto1fde@fd440000 {

		compatible = "qcom,qcrypto";

		reg = <0xfd440000 0x20000>,

		      <0xfd444000 0x9000>;

		reg-names = "crypto-base","crypto-bam-base";

		interrupts = <0 236 0>;

		qcom,bam-pipe-pair = <2>;

		qcom,ce-hw-instance = <0>;

		qcom,ce-hw-instance = <1>;

		qcom,ce-device = <0>;

		qcom,msm-bus,name = "qcrypto-noc";

		qcom,msm-bus,num-cases = <2>;
@@ -2460,7 +2460,59 @@ 
		qcom,msm-bus,vectors-KBps =

				<55 512 0 0>,

				<55 512 3936000 393600>;

		clock-names = "core_clk", "iface_clk", "bus_clk";

		clock-names = "core_clk_src", "iface_clk", "bus_clk";

		clocks = <&clock_rpm clk_qcrypto_ce2_clk>,

			 <&clock_rpm clk_gcc_ce2_ahb_m_clk>,

			 <&clock_rpm clk_gcc_ce2_axi_m_clk>;

		qcom,use-sw-aes-cbc-ecb-ctr-algo;

		qcom,use-sw-aes-xts-algo;

		qcom,use-sw-aes-ccm-algo;

		qcom,use-sw-ahash-algo;

		status = "disabled";

	};



	qcom_crypto2fde: qcrypto2fde@0xfd3c0000  {

		compatible = "qcom,qcrypto";

		reg = <0xfd3c0000  0x20000>,

		      <0xfd3c4000 0x9000>;

		reg-names = "crypto-base","crypto-bam-base";

		interrupts = <0 297 0>;

		qcom,bam-pipe-pair = <2>;

		qcom,ce-hw-instance = <2>;

		qcom,ce-device = <0>;

		qcom,msm-bus,name = "qcrypto-noc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<55 512 0 0>,

				<55 512 3936000 393600>;

		clock-names = "core_clk_src", "iface_clk", "bus_clk";

		clocks = <&clock_rpm clk_qcrypto_ce3_clk>,

			 <&clock_rpm clk_gcc_ce3_ahb_m_clk>,

			 <&clock_rpm clk_gcc_ce3_axi_m_clk>;

		qcom,use-sw-aes-cbc-ecb-ctr-algo;

		qcom,use-sw-aes-xts-algo;

		qcom,use-sw-aes-ccm-algo;

		qcom,use-sw-ahash-algo;

		status = "disabled";

	};



	qcom_crypto1pfe: qcrypto1pfe@fd440000 {

		compatible = "qcom,qcrypto";

		reg = <0xfd440000 0x20000>,

		      <0xfd444000 0x9000>;

		reg-names = "crypto-base","crypto-bam-base";

		interrupts = <0 236 0>;

		qcom,bam-pipe-pair = <0>;

		qcom,ce-hw-instance = <1>;

		qcom,ce-device = <1>;

		qcom,msm-bus,name = "qcrypto-noc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<55 512 0 0>,

				<55 512 3936000 393600>;

		clock-names = "core_clk_src", "iface_clk", "bus_clk";

		clocks = <&clock_rpm clk_qcrypto_ce2_clk>,

			 <&clock_rpm clk_gcc_ce2_ahb_m_clk>,

			 <&clock_rpm clk_gcc_ce2_axi_m_clk>;
@@ -2471,6 +2523,32 @@ 
		status = "disabled";

	};



	qcom_crypto2pfe: qcrypto2pfe@0xfd3c0000  {

		compatible = "qcom,qcrypto";

		reg = <0xfd3c0000  0x20000>,

		      <0xfd3c4000 0x9000>;

		reg-names = "crypto-base","crypto-bam-base";

		interrupts = <0 297 0>;

		qcom,bam-pipe-pair = <0>;

		qcom,ce-hw-instance = <2>;

		qcom,ce-device = <1>;

		qcom,msm-bus,name = "qcrypto-noc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<55 512 0 0>,

				<55 512 3936000 393600>;

		clock-names = "core_clk_src", "iface_clk", "bus_clk";

		clocks = <&clock_rpm clk_qcrypto_ce3_clk>,

			 <&clock_rpm clk_gcc_ce3_ahb_m_clk>,

			 <&clock_rpm clk_gcc_ce3_axi_m_clk>;

		qcom,use-sw-aes-cbc-ecb-ctr-algo;

		qcom,use-sw-aes-xts-algo;

		qcom,use-sw-aes-ccm-algo;

		qcom,use-sw-ahash-algo;

		status = "disabled";

	};



	qcom_cedev: qcedev@fd440000 {

		compatible = "qcom,qcedev";

		reg = <0xfd440000 0x20000>,
@@ -2486,7 +2564,7 @@ 
		qcom,msm-bus,vectors-KBps =

				<55 512 0 0>,

				<55 512 3936000 393600>;

		clock-names = "core_clk", "iface_clk", "bus_clk";

		clock-names = "core_clk_src", "iface_clk", "bus_clk";

		clocks = <&clock_rpm clk_qcedev_ce2_clk>,

			 <&clock_rpm clk_gcc_ce2_ahb_m_clk>,

			 <&clock_rpm clk_gcc_ce2_axi_m_clk>;
@@ -2499,7 +2577,9 @@ 
		reg-names = "secapp-region";

		qcom,disk-encrypt-pipe-pair = <2>;

		qcom,file-encrypt-pipe-pair = <0>;

		qcom,hlos-ce-hw-instance = <1>;

		qcom,support-multiple-ce-hw-instance;

		qcom,hlos-num-ce-hw-instances = <2>;

		qcom,hlos-ce-hw-instance = <1 2>;

		qcom,qsee-ce-hw-instance = <0>;

		qcom,msm-bus,name = "qseecom-noc";

		qcom,msm-bus,num-cases = <4>;