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Commit 41c594ab authored by Ralf Baechle's avatar Ralf Baechle
Browse files

[MIPS] MT: Improved multithreading support. 


    
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 2600990e

arch/mips/Kconfig

+5 −1
Original line number Diff line number Diff line
@@ -1447,6 +1447,10 @@ choice 
	prompt "MIPS MT options"

	depends on MIPS_MT



config MIPS_MT_SMTC

	bool "SMTC: Use all TCs on all VPEs for SMP"

	select SMP



config MIPS_MT_SMP

	bool "Use 1 TC on each available VPE for SMP"

	select SMP
@@ -1613,7 +1617,7 @@ source "mm/Kconfig" 


config SMP

	bool "Multi-Processing support"

	depends on CPU_RM9000 || ((SIBYTE_BCM1x80 || SIBYTE_BCM1x55 || SIBYTE_SB1250 || QEMU) && !SIBYTE_STANDALONE) || SGI_IP27 || MIPS_MT_SMP

	depends on CPU_RM9000 || ((SIBYTE_BCM1x80 || SIBYTE_BCM1x55 || SIBYTE_SB1250 || QEMU) && !SIBYTE_STANDALONE) || SGI_IP27 || MIPS_MT_SMP || MIPS_MT_SMTC

	---help---

	  This enables support for systems with more than one CPU. If you have

	  a system with only one CPU, like most personal computers, say N. If

arch/mips/kernel/Makefile

+3 −1
Original line number Diff line number Diff line
@@ -34,7 +34,9 @@ obj-$(CONFIG_CPU_R6000) += r6000_fpu.o r4k_switch.o 


obj-$(CONFIG_SMP)		+= smp.o



obj-$(CONFIG_MIPS_MT_SMP)	+= smp_mt.o

obj-$(CONFIG_MIPS_MT)		+= mips-mt.o

obj-$(CONFIG_MIPS_MT_SMTC)	+= smtc.o smtc-asm.o smtc-proc.o

obj-$(CONFIG_MIPS_MT_SMP)	+= smp-mt.o



obj-$(CONFIG_MIPS_APSP_KSPD)	+= kspd.o

obj-$(CONFIG_MIPS_VPE_LOADER)	+= vpe.o

arch/mips/kernel/asm-offsets.c

+3 −0
Original line number Diff line number Diff line
@@ -69,6 +69,9 @@ void output_ptreg_defines(void) 
	offset("#define PT_BVADDR ", struct pt_regs, cp0_badvaddr);

	offset("#define PT_STATUS ", struct pt_regs, cp0_status);

	offset("#define PT_CAUSE  ", struct pt_regs, cp0_cause);

#ifdef CONFIG_MIPS_MT_SMTC

	offset("#define PT_TCSTATUS  ", struct pt_regs, cp0_tcstatus);

#endif /* CONFIG_MIPS_MT_SMTC */

	size("#define PT_SIZE   ", struct pt_regs);

	linefeed;

}

arch/mips/kernel/entry.S

+34 −0
Original line number Diff line number Diff line
@@ -17,6 +17,9 @@ 
#include <asm/isadep.h>

#include <asm/thread_info.h>

#include <asm/war.h>

#ifdef CONFIG_MIPS_MT_SMTC

#include <asm/mipsmtregs.h>

#endif



#ifdef CONFIG_PREEMPT

	.macro	preempt_stop
@@ -75,6 +78,37 @@ FEXPORT(syscall_exit) 
	bnez	t0, syscall_exit_work



FEXPORT(restore_all)			# restore full frame

#ifdef CONFIG_MIPS_MT_SMTC

/* Detect and execute deferred IPI "interrupts" */

	move	a0,sp

	jal	deferred_smtc_ipi

/* Re-arm any temporarily masked interrupts not explicitly "acked" */

	mfc0	v0, CP0_TCSTATUS

	ori	v1, v0, TCSTATUS_IXMT

	mtc0	v1, CP0_TCSTATUS

	andi	v0, TCSTATUS_IXMT

	ehb

	mfc0	t0, CP0_TCCONTEXT

	DMT	9				# dmt t1

	jal	mips_ihb

	mfc0	t2, CP0_STATUS

	andi	t3, t0, 0xff00

	or	t2, t2, t3

	mtc0	t2, CP0_STATUS

	ehb

	andi	t1, t1, VPECONTROL_TE

	beqz	t1, 1f

	EMT

1:

	mfc0	v1, CP0_TCSTATUS

	/* We set IXMT above, XOR should cler it here */

	xori	v1, v1, TCSTATUS_IXMT

	or	v1, v0, v1

	mtc0	v1, CP0_TCSTATUS

	ehb

	xor	t0, t0, t3

	mtc0	t0, CP0_TCCONTEXT

#endif /* CONFIG_MIPS_MT_SMTC */

	.set	noat

	RESTORE_TEMP

	RESTORE_AT

arch/mips/kernel/gdb-low.S

+23 −1
Original line number Diff line number Diff line
@@ -283,11 +283,33 @@ 
 */



3:

#ifdef CONFIG_MIPS_MT_SMTC

		/* Read-modify write of Status must be atomic */

		mfc0	t2, CP0_TCSTATUS

		ori	t1, t2, TCSTATUS_IXMT

		mtc0	t1, CP0_TCSTATUS

		andi	t2, t2, TCSTATUS_IXMT

		ehb

		DMT	9				# dmt	t1

		jal	mips_ihb

		nop

#endif /* CONFIG_MIPS_MT_SMTC */

		mfc0	t0, CP0_STATUS

		ori	t0, 0x1f

		xori	t0, 0x1f

		mtc0	t0, CP0_STATUS



#ifdef CONFIG_MIPS_MT_SMTC

        	andi    t1, t1, VPECONTROL_TE

        	beqz    t1, 9f

		nop

        	EMT					# emt

9:

		mfc0	t1, CP0_TCSTATUS

		xori	t1, t1, TCSTATUS_IXMT

		or	t1, t1, t2

		mtc0	t1, CP0_TCSTATUS

		ehb

#endif /* CONFIG_MIPS_MT_SMTC */

		LONG_L	v0, GDB_FR_STATUS(sp)

		LONG_L	v1, GDB_FR_EPC(sp)

		mtc0	v0, CP0_STATUS