Loading drivers/gpu/msm/Makefile +0 −1 Original line number Diff line number Diff line Loading @@ -7,7 +7,6 @@ msm_kgsl_core-y = \ kgsl_pwrctrl.o \ kgsl_pwrscale.o \ kgsl_mmu.o \ kgsl_gpummu.o \ kgsl_iommu.o \ kgsl_snapshot.o \ kgsl_events.o Loading drivers/gpu/msm/adreno.c +8 −63 Original line number Diff line number Diff line Loading @@ -45,38 +45,6 @@ /* Number of times to try hard reset */ #define NUM_TIMES_RESET_RETRY 5 /* Adreno MH arbiter config*/ #define ADRENO_CFG_MHARB \ (0x10 \ | (0 << MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY__SHIFT) \ | (1 << MH_ARBITER_CONFIG__L1_ARB_ENABLE__SHIFT) \ | (1 << MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE__SHIFT) \ | (0 << MH_ARBITER_CONFIG__L2_ARB_CONTROL__SHIFT) \ | (1 << MH_ARBITER_CONFIG__PAGE_SIZE__SHIFT) \ | (1 << MH_ARBITER_CONFIG__TC_REORDER_ENABLE__SHIFT) \ | (1 << MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE__SHIFT) \ | (0 << MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE__SHIFT) \ | (0x8 << MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT__SHIFT) \ | (1 << MH_ARBITER_CONFIG__CP_CLNT_ENABLE__SHIFT) \ | (1 << MH_ARBITER_CONFIG__VGT_CLNT_ENABLE__SHIFT) \ | (1 << MH_ARBITER_CONFIG__TC_CLNT_ENABLE__SHIFT) \ | (1 << MH_ARBITER_CONFIG__RB_CLNT_ENABLE__SHIFT) \ | (1 << MH_ARBITER_CONFIG__PA_CLNT_ENABLE__SHIFT)) #define ADRENO_MMU_CONFIG \ (0x01 \ | (MMU_CONFIG << MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR__SHIFT) \ | (MMU_CONFIG << MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR__SHIFT) \ | (MMU_CONFIG << MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR__SHIFT) \ | (MMU_CONFIG << MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR__SHIFT) \ | (MMU_CONFIG << MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR__SHIFT) \ | (MMU_CONFIG << MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR__SHIFT) \ | (MMU_CONFIG << MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR__SHIFT) \ | (MMU_CONFIG << MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR__SHIFT) \ | (MMU_CONFIG << MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR__SHIFT) \ | (MMU_CONFIG << MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR__SHIFT) \ | (MMU_CONFIG << MH_MMU_CONFIG__PA_W_CLNT_BEHAVIOR__SHIFT)) #define KGSL_LOG_LEVEL_DEFAULT 3 static void adreno_start_work(struct work_struct *work); Loading Loading @@ -113,9 +81,6 @@ static struct adreno_device device_3d0 = { ARRAY_SIZE(adreno_governors)), .name = DEVICE_3D0_NAME, .id = KGSL_DEVICE_3D0, .mmu = { .config = ADRENO_MMU_CONFIG, }, .pwrctrl = { .irq_name = KGSL_3D0_IRQ, }, Loading Loading @@ -868,14 +833,6 @@ static int adreno_setup_pt(struct kgsl_device *device, return result; } /* * Set the mpu end to the last "normal" global memory we use. * For the IOMMU, this will be used to restrict access to the * mapped registers. */ device->mh.mpu_range = adreno_dev->profile.shared_buffer.gpuaddr + adreno_dev->profile.shared_buffer.size; return 0; } Loading @@ -889,11 +846,6 @@ static unsigned int _adreno_iommu_setstate_v0(struct kgsl_device *device, struct adreno_device *adreno_dev = ADRENO_DEVICE(device); int i; if (cpu_is_msm8960()) cmds += adreno_add_change_mh_phys_limit_cmds(cmds, 0xFFFFF000, device->mmu.setstate_memory.gpuaddr + KGSL_IOMMU_SETSTATE_NOP_OFFSET); else cmds += adreno_add_bank_change_cmds(cmds, KGSL_IOMMU_CONTEXT_USER, device->mmu.setstate_memory.gpuaddr + Loading Loading @@ -971,13 +923,6 @@ static unsigned int _adreno_iommu_setstate_v0(struct kgsl_device *device, /* Release GPU-CPU sync Lock here */ cmds += kgsl_mmu_sync_unlock(&device->mmu, cmds); if (cpu_is_msm8960()) cmds += adreno_add_change_mh_phys_limit_cmds(cmds, kgsl_mmu_get_reg_gpuaddr(&device->mmu, 0, 0, KGSL_IOMMU_GLOBAL_BASE), device->mmu.setstate_memory.gpuaddr + KGSL_IOMMU_SETSTATE_NOP_OFFSET); else cmds += adreno_add_bank_change_cmds(cmds, KGSL_IOMMU_CONTEXT_PRIV, device->mmu.setstate_memory.gpuaddr + Loading drivers/gpu/msm/adreno.h +0 −13 Original line number Diff line number Diff line Loading @@ -157,7 +157,6 @@ struct adreno_device { size_t pm4_fw_size; unsigned int pm4_fw_version; struct adreno_ringbuffer ringbuffer; unsigned int mharb; struct adreno_gpudev *gpudev; unsigned int wait_timeout; unsigned int pm4_jt_idx; Loading Loading @@ -735,18 +734,6 @@ static inline int __adreno_add_idle_indirect_cmds(unsigned int *cmds, return 5; } static inline int adreno_add_change_mh_phys_limit_cmds(unsigned int *cmds, unsigned int new_phys_limit, unsigned int nop_gpuaddr) { unsigned int *start = cmds; *cmds++ = cp_type0_packet(MH_MMU_MPU_END, 1); *cmds++ = new_phys_limit; cmds += __adreno_add_idle_indirect_cmds(cmds, nop_gpuaddr); return cmds - start; } static inline int adreno_add_bank_change_cmds(unsigned int *cmds, int cur_ctx_bank, unsigned int nop_gpuaddr) Loading drivers/gpu/msm/kgsl.c +1 −20 Original line number Diff line number Diff line Loading @@ -52,7 +52,7 @@ MODULE_PARM_DESC(kgsl_pagetable_count, "Minimum number of pagetables for KGSL to allocate at initialization time"); module_param_named(mmutype, ksgl_mmu_type, charp, 0); MODULE_PARM_DESC(ksgl_mmu_type, "Type of MMU to be used for graphics. Valid values are 'iommu' or 'gpummu' or 'nommu'"); "Type of MMU to be used for graphics. Valid values are 'iommu' or 'nommu'"); struct kgsl_dma_buf_meta { struct dma_buf_attachment *attach; Loading Loading @@ -4200,21 +4200,8 @@ void kgsl_device_platform_remove(struct kgsl_device *device) } EXPORT_SYMBOL(kgsl_device_platform_remove); static int kgsl_ptdata_init(void) { kgsl_driver.ptpool = kgsl_mmu_ptpool_init(kgsl_pagetable_count); if (!kgsl_driver.ptpool) return -ENOMEM; return 0; } static void kgsl_core_exit(void) { kgsl_mmu_ptpool_destroy(kgsl_driver.ptpool); kgsl_driver.ptpool = NULL; kgsl_drm_exit(); kgsl_cffdump_destroy(); kgsl_core_debugfs_close(); Loading Loading @@ -4301,12 +4288,6 @@ static int __init kgsl_core_init(void) kgsl_mmu_set_mmutype(ksgl_mmu_type); if (KGSL_MMU_TYPE_GPU == kgsl_mmu_get_mmutype()) { result = kgsl_ptdata_init(); if (result) goto err; } if (kgsl_memfree_hist_init()) KGSL_CORE_ERR("failed to init memfree_hist"); Loading drivers/gpu/msm/kgsl.h +0 −2 Original line number Diff line number Diff line Loading @@ -118,8 +118,6 @@ struct kgsl_driver { /* Mutex for protecting the device list */ struct mutex devlock; void *ptpool; struct mutex memfree_hist_mutex; struct kgsl_memfree_hist memfree_hist; Loading Loading
drivers/gpu/msm/Makefile +0 −1 Original line number Diff line number Diff line Loading @@ -7,7 +7,6 @@ msm_kgsl_core-y = \ kgsl_pwrctrl.o \ kgsl_pwrscale.o \ kgsl_mmu.o \ kgsl_gpummu.o \ kgsl_iommu.o \ kgsl_snapshot.o \ kgsl_events.o Loading
drivers/gpu/msm/adreno.c +8 −63 Original line number Diff line number Diff line Loading @@ -45,38 +45,6 @@ /* Number of times to try hard reset */ #define NUM_TIMES_RESET_RETRY 5 /* Adreno MH arbiter config*/ #define ADRENO_CFG_MHARB \ (0x10 \ | (0 << MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY__SHIFT) \ | (1 << MH_ARBITER_CONFIG__L1_ARB_ENABLE__SHIFT) \ | (1 << MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE__SHIFT) \ | (0 << MH_ARBITER_CONFIG__L2_ARB_CONTROL__SHIFT) \ | (1 << MH_ARBITER_CONFIG__PAGE_SIZE__SHIFT) \ | (1 << MH_ARBITER_CONFIG__TC_REORDER_ENABLE__SHIFT) \ | (1 << MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE__SHIFT) \ | (0 << MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE__SHIFT) \ | (0x8 << MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT__SHIFT) \ | (1 << MH_ARBITER_CONFIG__CP_CLNT_ENABLE__SHIFT) \ | (1 << MH_ARBITER_CONFIG__VGT_CLNT_ENABLE__SHIFT) \ | (1 << MH_ARBITER_CONFIG__TC_CLNT_ENABLE__SHIFT) \ | (1 << MH_ARBITER_CONFIG__RB_CLNT_ENABLE__SHIFT) \ | (1 << MH_ARBITER_CONFIG__PA_CLNT_ENABLE__SHIFT)) #define ADRENO_MMU_CONFIG \ (0x01 \ | (MMU_CONFIG << MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR__SHIFT) \ | (MMU_CONFIG << MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR__SHIFT) \ | (MMU_CONFIG << MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR__SHIFT) \ | (MMU_CONFIG << MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR__SHIFT) \ | (MMU_CONFIG << MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR__SHIFT) \ | (MMU_CONFIG << MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR__SHIFT) \ | (MMU_CONFIG << MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR__SHIFT) \ | (MMU_CONFIG << MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR__SHIFT) \ | (MMU_CONFIG << MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR__SHIFT) \ | (MMU_CONFIG << MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR__SHIFT) \ | (MMU_CONFIG << MH_MMU_CONFIG__PA_W_CLNT_BEHAVIOR__SHIFT)) #define KGSL_LOG_LEVEL_DEFAULT 3 static void adreno_start_work(struct work_struct *work); Loading Loading @@ -113,9 +81,6 @@ static struct adreno_device device_3d0 = { ARRAY_SIZE(adreno_governors)), .name = DEVICE_3D0_NAME, .id = KGSL_DEVICE_3D0, .mmu = { .config = ADRENO_MMU_CONFIG, }, .pwrctrl = { .irq_name = KGSL_3D0_IRQ, }, Loading Loading @@ -868,14 +833,6 @@ static int adreno_setup_pt(struct kgsl_device *device, return result; } /* * Set the mpu end to the last "normal" global memory we use. * For the IOMMU, this will be used to restrict access to the * mapped registers. */ device->mh.mpu_range = adreno_dev->profile.shared_buffer.gpuaddr + adreno_dev->profile.shared_buffer.size; return 0; } Loading @@ -889,11 +846,6 @@ static unsigned int _adreno_iommu_setstate_v0(struct kgsl_device *device, struct adreno_device *adreno_dev = ADRENO_DEVICE(device); int i; if (cpu_is_msm8960()) cmds += adreno_add_change_mh_phys_limit_cmds(cmds, 0xFFFFF000, device->mmu.setstate_memory.gpuaddr + KGSL_IOMMU_SETSTATE_NOP_OFFSET); else cmds += adreno_add_bank_change_cmds(cmds, KGSL_IOMMU_CONTEXT_USER, device->mmu.setstate_memory.gpuaddr + Loading Loading @@ -971,13 +923,6 @@ static unsigned int _adreno_iommu_setstate_v0(struct kgsl_device *device, /* Release GPU-CPU sync Lock here */ cmds += kgsl_mmu_sync_unlock(&device->mmu, cmds); if (cpu_is_msm8960()) cmds += adreno_add_change_mh_phys_limit_cmds(cmds, kgsl_mmu_get_reg_gpuaddr(&device->mmu, 0, 0, KGSL_IOMMU_GLOBAL_BASE), device->mmu.setstate_memory.gpuaddr + KGSL_IOMMU_SETSTATE_NOP_OFFSET); else cmds += adreno_add_bank_change_cmds(cmds, KGSL_IOMMU_CONTEXT_PRIV, device->mmu.setstate_memory.gpuaddr + Loading
drivers/gpu/msm/adreno.h +0 −13 Original line number Diff line number Diff line Loading @@ -157,7 +157,6 @@ struct adreno_device { size_t pm4_fw_size; unsigned int pm4_fw_version; struct adreno_ringbuffer ringbuffer; unsigned int mharb; struct adreno_gpudev *gpudev; unsigned int wait_timeout; unsigned int pm4_jt_idx; Loading Loading @@ -735,18 +734,6 @@ static inline int __adreno_add_idle_indirect_cmds(unsigned int *cmds, return 5; } static inline int adreno_add_change_mh_phys_limit_cmds(unsigned int *cmds, unsigned int new_phys_limit, unsigned int nop_gpuaddr) { unsigned int *start = cmds; *cmds++ = cp_type0_packet(MH_MMU_MPU_END, 1); *cmds++ = new_phys_limit; cmds += __adreno_add_idle_indirect_cmds(cmds, nop_gpuaddr); return cmds - start; } static inline int adreno_add_bank_change_cmds(unsigned int *cmds, int cur_ctx_bank, unsigned int nop_gpuaddr) Loading
drivers/gpu/msm/kgsl.c +1 −20 Original line number Diff line number Diff line Loading @@ -52,7 +52,7 @@ MODULE_PARM_DESC(kgsl_pagetable_count, "Minimum number of pagetables for KGSL to allocate at initialization time"); module_param_named(mmutype, ksgl_mmu_type, charp, 0); MODULE_PARM_DESC(ksgl_mmu_type, "Type of MMU to be used for graphics. Valid values are 'iommu' or 'gpummu' or 'nommu'"); "Type of MMU to be used for graphics. Valid values are 'iommu' or 'nommu'"); struct kgsl_dma_buf_meta { struct dma_buf_attachment *attach; Loading Loading @@ -4200,21 +4200,8 @@ void kgsl_device_platform_remove(struct kgsl_device *device) } EXPORT_SYMBOL(kgsl_device_platform_remove); static int kgsl_ptdata_init(void) { kgsl_driver.ptpool = kgsl_mmu_ptpool_init(kgsl_pagetable_count); if (!kgsl_driver.ptpool) return -ENOMEM; return 0; } static void kgsl_core_exit(void) { kgsl_mmu_ptpool_destroy(kgsl_driver.ptpool); kgsl_driver.ptpool = NULL; kgsl_drm_exit(); kgsl_cffdump_destroy(); kgsl_core_debugfs_close(); Loading Loading @@ -4301,12 +4288,6 @@ static int __init kgsl_core_init(void) kgsl_mmu_set_mmutype(ksgl_mmu_type); if (KGSL_MMU_TYPE_GPU == kgsl_mmu_get_mmutype()) { result = kgsl_ptdata_init(); if (result) goto err; } if (kgsl_memfree_hist_init()) KGSL_CORE_ERR("failed to init memfree_hist"); Loading
drivers/gpu/msm/kgsl.h +0 −2 Original line number Diff line number Diff line Loading @@ -118,8 +118,6 @@ struct kgsl_driver { /* Mutex for protecting the device list */ struct mutex devlock; void *ptpool; struct mutex memfree_hist_mutex; struct kgsl_memfree_hist memfree_hist; Loading