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Commit 40394ea7 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Config I2C on BLSP1 QUP5 for 8916"

parents e694bc89 9b2e764b

Documentation/devicetree/bindings/i2c/i2c-msm-v2.txt

+2 −2
Original line number Diff line number Diff line
@@ -6,7 +6,7 @@ Required properties: 
 - reg-names : Register region name(s) referenced in reg above

	"qup_phys_addr" : Physical address of QUP register space.

	"bam_phys_addr" : Physical address of BAM for this controller.

 - compatible : should be "qcom,i2c-qup"

 - compatible : should be "qcom,i2c-msm-v2"

 - interrupts : Interrupt number which correspond to the entry with the same

	index in interrupt-names.

 - interrupt-names: QUP core interrupt name(s) referenced in interrupts above
@@ -40,7 +40,7 @@ Example: 
	};



	i2c_10: i2c@f9966000 {

		compatible = "qcom,msm-i2c-v2";

		compatible = "qcom,i2c-msm-v2";

		reg-names = "qup_phys_addr", "bam_phys_addr";

		reg = <0xf9966000 0x1000>,

		      <0xf9904000 0x10000>;

arch/arm/boot/dts/qcom/msm8916-pinctrl.dtsi

+18 −0
Original line number Diff line number Diff line
@@ -243,6 +243,24 @@ 
			};

		};



		pmx_i2c_5 {

			/* CLK, DATA */

			qcom,pins = <&gp 19>, <&gp 18>;

			qcom,num-grp-pins = <2>;

			qcom,pin-func = <2>;

			label = "pmx_i2c_5";



			i2c_5_active: i2c_5_active {

				drive-strength = <2>; /* 2 MA */

				bias-disable = <0>; /* No PULL */

			};



			i2c_5_sleep: i2c_5_sleep {

				drive-strength = <2>; /* 2 MA */

				bias-disable = <0>; /* No PULL */

			};

		};



		/* QDSD pin type */

		qdsd: qdsd {

			qcom,pin-type-qdsd;

arch/arm/boot/dts/qcom/msm8916.dtsi

+23 −0
Original line number Diff line number Diff line
@@ -38,6 +38,7 @@ 


		spi0 = &spi_0; /* SPI0 controller device */

		i2c0 = &i2c_0; /* I2C0 controller device */

		i2c5 = &i2c_5; /* I2C5 controller device */

	};



	cpus {
@@ -1162,6 +1163,28 @@ 
		qcom,master-id = <86>;

	};



	i2c_5: i2c@78b9000 { /* BLSP1 QUP5 */

		compatible = "qcom,i2c-msm-v2";

		reg-names = "qup_phys_addr", "bam_phys_addr";

		reg = <0x78b9000 0x600>,

		      <0x7884000 0x23000>;

		interrupt-names = "qup_irq", "bam_irq";

		interrupts = <0 99 0>, <0 238 0>;

		clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,

			 <&clock_gcc clk_gcc_blsp1_qup5_i2c_apps_clk>;

		clock-names = "iface_clk", "core_clk";

		qcom,clk-freq-out = <100000>;

		qcom,clk-freq-in  = <19200000>;

		pinctrl-names = "i2c_active", "i2c_sleep";

		pinctrl-0 = <&i2c_5_active>;

		pinctrl-1 = <&i2c_5_sleep>;

		qcom,noise-rjct-scl = <0>;

		qcom,noise-rjct-sda = <0>;

		qcom,bam-pipe-idx-cons = <12>;

		qcom,bam-pipe-idx-prod = <13>;

		qcom,master-id = <86>;

	};



	spmi_bus: qcom,spmi@200f000 {

		compatible = "qcom,spmi-pmic-arb";

		reg = <0x200f000 0x1000>,