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Commit 402a576f authored by Carter Cooper's avatar Carter Cooper
Browse files

msm: kgsl: Uncross adreno_device and kgsl_device streams 



Adreno should deal with adreno_devices and not kgsl_devices. Keep
usage more uniform across our devices.

Change-Id: Iccc06671d7a9653e16bdc71fdab4ff9145f60d55
Signed-off-by: default avatarCarter Cooper <ccooper@codeaurora.org>
parent d809efea

drivers/gpu/msm/adreno.c

+11 −12
Original line number Diff line number Diff line
@@ -825,7 +825,7 @@ static unsigned int _adreno_iommu_setstate_v0(struct kgsl_device *device, 
			 * Read back the ttbr0 register as a barrier to ensure

			 * above writes have completed

			 */

			cmds += adreno_add_read_cmds(device, cmds,

			cmds += adreno_add_read_cmds(cmds,

				kgsl_mmu_get_reg_gpuaddr(&device->mmu, i,

				KGSL_IOMMU_CONTEXT_USER, KGSL_IOMMU_CTX_TTBR0),

				reg_pt_val,
@@ -854,7 +854,7 @@ static unsigned int _adreno_iommu_setstate_v0(struct kgsl_device *device, 
			device->mmu.setstate_memory.gpuaddr +

			KGSL_IOMMU_SETSTATE_NOP_OFFSET);



			cmds += adreno_add_read_cmds(device, cmds,

			cmds += adreno_add_read_cmds(cmds,

				kgsl_mmu_get_reg_gpuaddr(&device->mmu, i,

					KGSL_IOMMU_CONTEXT_USER,

					KGSL_IOMMU_CTX_TTBR0),
@@ -1752,8 +1752,8 @@ int adreno_probe(struct platform_device *pdev) 
	if (status)

		goto out;



	adreno_debugfs_init(device);

	adreno_profile_init(device);

	adreno_debugfs_init(adreno_dev);

	adreno_profile_init(adreno_dev);



	adreno_init_sysfs(device);
@@ -1794,8 +1794,8 @@ static int adreno_remove(struct platform_device *pdev) 
#endif

	adreno_uninit_sysfs(device);



	adreno_coresight_remove(device);

	adreno_profile_close(device);

	adreno_coresight_remove(adreno_dev);

	adreno_profile_close(adreno_dev);



	kgsl_pwrscale_close(device);
@@ -1833,7 +1833,7 @@ static int adreno_init(struct kgsl_device *device) 
	adreno_wq = alloc_workqueue("adreno", 0, 1);



	/* Initialize coresight for the target */

	adreno_coresight_init(device);

	adreno_coresight_init(adreno_dev);



	adreno_ringbuffer_read_pm4_ucode(device);

	adreno_ringbuffer_read_pfp_ucode(device);
@@ -2845,15 +2845,14 @@ static int adreno_setproperty(struct kgsl_device_private *dev_priv, 


/**

 * adreno_hw_isidle() - Check if the GPU core is idle

 * @device: Pointer to the adreno device structure for the GPU

 * @adreno_dev: Pointer to the Adreno device structure for the GPU

 *

 * Return true if the RBBM status register for the GPU type indicates that the

 * hardware is idle

 */

bool adreno_hw_isidle(struct kgsl_device *device)

bool adreno_hw_isidle(struct adreno_device *adreno_dev)

{

	unsigned int reg_rbbm_status;

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);



	adreno_readreg(adreno_dev, ADRENO_REG_RBBM_STATUS,
@@ -2979,7 +2978,7 @@ bool adreno_isidle(struct kgsl_device *device) 
	}



	if (i == adreno_dev->num_ringbuffers)

		return adreno_hw_isidle(device);

		return adreno_hw_isidle(adreno_dev);



	return false;

}
@@ -3071,7 +3070,7 @@ static int adreno_suspend_context(struct kgsl_device *device) 
	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);



	/* process any profiling results that are available */

	adreno_profile_process_results(device);

	adreno_profile_process_results(adreno_dev);



	/* switch to NULL ctxt */

	if (adreno_dev->drawctxt_active != NULL) {

drivers/gpu/msm/adreno.h

+22 −24
Original line number Diff line number Diff line
@@ -770,14 +770,14 @@ int adreno_perfcounter_put(struct adreno_device *adreno_dev, 


int adreno_a3xx_pwron_fixup_init(struct adreno_device *adreno_dev);



int adreno_coresight_init(struct kgsl_device *device);

int adreno_coresight_init(struct adreno_device *adreno_dev);



void adreno_coresight_start(struct adreno_device *adreno_dev);

void adreno_coresight_stop(struct adreno_device *adreno_dev);



void adreno_coresight_remove(struct kgsl_device *device);

void adreno_coresight_remove(struct adreno_device *adreno_dev);



bool adreno_hw_isidle(struct kgsl_device *device);

bool adreno_hw_isidle(struct adreno_device *adreno_dev);



int adreno_rb_readtimestamp(struct kgsl_device *device,

	void *priv, enum kgsl_timestamp_type type,
@@ -904,14 +904,13 @@ static inline int adreno_add_bank_change_cmds(unsigned int *cmds, 


/*

 * adreno_read_cmds - Add pm4 packets to perform read

 * @device - Pointer to device structure

 * @cmds - Pointer to memory where read commands need to be added

 * @addr - gpu address of the read

 * @val - The GPU will wait until the data at address addr becomes

 * @nop_gpuaddr - NOP GPU address

 * equal to value

 */

static inline int adreno_add_read_cmds(struct kgsl_device *device,

				unsigned int *cmds, unsigned int addr,

static inline int adreno_add_read_cmds(unsigned int *cmds, unsigned int addr,

				unsigned int val, unsigned int nop_gpuaddr)

{

	unsigned int *start = cmds;
@@ -1029,10 +1028,9 @@ static inline void adreno_readreg(struct adreno_device *adreno_dev, 
				enum adreno_regs offset_name, unsigned int *val)

{

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	struct kgsl_device *device = &adreno_dev->dev;

	if (adreno_checkreg_off(adreno_dev, offset_name))

		kgsl_regread(device, gpudev->reg_offsets->offsets[offset_name],

			val);

		kgsl_regread(&adreno_dev->dev,

				gpudev->reg_offsets->offsets[offset_name], val);

}



/*
@@ -1046,10 +1044,9 @@ static inline void adreno_writereg(struct adreno_device *adreno_dev, 
				enum adreno_regs offset_name, unsigned int val)

{

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	struct kgsl_device *device = &adreno_dev->dev;

	if (adreno_checkreg_off(adreno_dev, offset_name))

		kgsl_regwrite(device, gpudev->reg_offsets->offsets[offset_name],

			val);

		kgsl_regwrite(&adreno_dev->dev,

				gpudev->reg_offsets->offsets[offset_name], val);

}



/*
@@ -1151,18 +1148,17 @@ static inline void adreno_put_gpu_halt(struct adreno_device *adreno_dev) 


/*

 * adreno_vbif_start() - Program VBIF registers, called in device start

 * @device: Pointer to device whose vbif data is to be programmed

 * @adreno_dev: Pointer to device whose vbif data is to be programmed

 * @vbif_platforms: list register value pair of vbif for a family

 * of adreno cores

 * @num_platforms: Number of platforms contained in vbif_platforms

 */

static inline void adreno_vbif_start(struct kgsl_device *device,

static inline void adreno_vbif_start(struct adreno_device *adreno_dev,

			const struct adreno_vbif_platform *vbif_platforms,

			int num_platforms)

{

	int i;

	const struct adreno_vbif_data *vbif = NULL;

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);



	for (i = 0; i < num_platforms; i++) {

		if (vbif_platforms[i].devfunc(adreno_dev)) {
@@ -1172,7 +1168,7 @@ static inline void adreno_vbif_start(struct kgsl_device *device, 
	}

	BUG_ON(vbif == NULL);

	while (vbif->reg != 0) {

		kgsl_regwrite(device, vbif->reg, vbif->val);

		kgsl_regwrite(&adreno_dev->dev, vbif->reg, vbif->val);

		vbif++;

	}

}
@@ -1180,7 +1176,7 @@ static inline void adreno_vbif_start(struct kgsl_device *device, 
/**

 * adreno_set_protected_registers() - Protect the specified range of registers

 * from being accessed by the GPU

 * @device: pointer to the KGSL device

 * @adreno_dev: pointer to the Adreno device

 * @index: Pointer to the index of the protect mode register to write to

 * @reg: Starting dword register to write

 * @mask_len: Size of the mask to protect (# of registers = 2 ** mask_len)
@@ -1192,11 +1188,11 @@ static inline void adreno_vbif_start(struct kgsl_device *device, 
 * pointer for each range and the registers will be magically programmed in

 * incremental fashion

 */

static inline void adreno_set_protected_registers(struct kgsl_device *device,

	unsigned int *index, unsigned int reg, int mask_len)

static inline void adreno_set_protected_registers(

		struct adreno_device *adreno_dev, unsigned int *index,

		unsigned int reg, int mask_len)

{

	unsigned int val;

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);



	/* A430 has 24 registers (yay!).  Everything else has 16 (boo!) */
@@ -1213,18 +1209,20 @@ static inline void adreno_set_protected_registers(struct kgsl_device *device, 
	 */



	if (adreno_is_a4xx(adreno_dev))

		kgsl_regwrite(device, A4XX_CP_PROTECT_REG_0 + *index, val);

		kgsl_regwrite(&adreno_dev->dev,

				A4XX_CP_PROTECT_REG_0 + *index, val);

	else if (adreno_is_a3xx(adreno_dev))

		kgsl_regwrite(device, A3XX_CP_PROTECT_REG_0 + *index, val);

		kgsl_regwrite(&adreno_dev->dev,

				A3XX_CP_PROTECT_REG_0 + *index, val);

	*index = *index + 1;

}



#ifdef CONFIG_DEBUG_FS

void adreno_debugfs_init(struct kgsl_device *device);

void adreno_debugfs_init(struct adreno_device *adreno_dev);

void adreno_context_debugfs_init(struct adreno_device *,

				struct adreno_context *);

#else

static inline void adreno_debugfs_init(struct kgsl_device *device) { }

static inline void adreno_debugfs_init(struct adreno_device *adreno_dev) { }

static inline void adreno_context_debugfs_init(struct adreno_device *device,

						struct adreno_context *context)

						{ }

drivers/gpu/msm/adreno_a3xx.c

+21 −20
Original line number Diff line number Diff line
@@ -2195,12 +2195,13 @@ int a3xx_perfcounter_init(struct adreno_device *adreno_dev) 


/**

 * a3xx_protect_init() - Initializes register protection on a3xx

 * @device: Pointer to the device structure

 * @adreno_dev: Pointer to the device structure

 * Performs register writes to enable protected access to sensitive

 * registers

 */

static void a3xx_protect_init(struct kgsl_device *device)

static void a3xx_protect_init(struct adreno_device *adreno_dev)

{

	struct kgsl_device *device = &adreno_dev->dev;

	int index = 0;

	struct kgsl_protected_registers *iommu_regs;
@@ -2208,32 +2209,32 @@ static void a3xx_protect_init(struct kgsl_device *device) 
	kgsl_regwrite(device, A3XX_CP_PROTECT_CTRL, 0x00000007);



	/* RBBM registers */

	adreno_set_protected_registers(device, &index, 0x18, 0);

	adreno_set_protected_registers(device, &index, 0x20, 2);

	adreno_set_protected_registers(device, &index, 0x33, 0);

	adreno_set_protected_registers(device, &index, 0x42, 0);

	adreno_set_protected_registers(device, &index, 0x50, 4);

	adreno_set_protected_registers(device, &index, 0x63, 0);

	adreno_set_protected_registers(device, &index, 0x100, 4);

	adreno_set_protected_registers(adreno_dev, &index, 0x18, 0);

	adreno_set_protected_registers(adreno_dev, &index, 0x20, 2);

	adreno_set_protected_registers(adreno_dev, &index, 0x33, 0);

	adreno_set_protected_registers(adreno_dev, &index, 0x42, 0);

	adreno_set_protected_registers(adreno_dev, &index, 0x50, 4);

	adreno_set_protected_registers(adreno_dev, &index, 0x63, 0);

	adreno_set_protected_registers(adreno_dev, &index, 0x100, 4);



	/* CP registers */

	adreno_set_protected_registers(device, &index, 0x1C0, 5);

	adreno_set_protected_registers(device, &index, 0x1EC, 1);

	adreno_set_protected_registers(device, &index, 0x1F6, 1);

	adreno_set_protected_registers(device, &index, 0x1F8, 2);

	adreno_set_protected_registers(device, &index, 0x45E, 2);

	adreno_set_protected_registers(device, &index, 0x460, 4);

	adreno_set_protected_registers(adreno_dev, &index, 0x1C0, 5);

	adreno_set_protected_registers(adreno_dev, &index, 0x1EC, 1);

	adreno_set_protected_registers(adreno_dev, &index, 0x1F6, 1);

	adreno_set_protected_registers(adreno_dev, &index, 0x1F8, 2);

	adreno_set_protected_registers(adreno_dev, &index, 0x45E, 2);

	adreno_set_protected_registers(adreno_dev, &index, 0x460, 4);



	/* RB registers */

	adreno_set_protected_registers(device, &index, 0xCC0, 0);

	adreno_set_protected_registers(adreno_dev, &index, 0xCC0, 0);



	/* VBIF registers */

	adreno_set_protected_registers(device, &index, 0x3000, 6);

	adreno_set_protected_registers(adreno_dev, &index, 0x3000, 6);



	/* SMMU registers */

	iommu_regs = kgsl_mmu_get_prot_regs(&device->mmu);

	if (iommu_regs)

		adreno_set_protected_registers(device, &index,

		adreno_set_protected_registers(adreno_dev, &index,

				iommu_regs->base, iommu_regs->range);

}
@@ -2241,7 +2242,7 @@ static void a3xx_start(struct adreno_device *adreno_dev) 
{

	struct kgsl_device *device = &adreno_dev->dev;



	adreno_vbif_start(device, a3xx_vbif_platforms,

	adreno_vbif_start(adreno_dev, a3xx_vbif_platforms,

			ARRAY_SIZE(a3xx_vbif_platforms));



	/* Make all blocks contribute to the GPU BUSY perf counter */
@@ -2293,7 +2294,7 @@ static void a3xx_start(struct adreno_device *adreno_dev) 
			(unsigned int)(adreno_dev->gmem_base >> 14));



	/* Turn on protection */

	a3xx_protect_init(device);

	a3xx_protect_init(adreno_dev);



	/* Turn on performance counters */

	kgsl_regwrite(device, A3XX_RBBM_PERFCTR_CTL, 0x01);

drivers/gpu/msm/adreno_a4xx.c

+19 −18
Original line number Diff line number Diff line
@@ -494,50 +494,51 @@ static void a4xx_enable_hwcg(struct kgsl_device *device) 


/**

 * a4xx_protect_init() - Initializes register protection on a4xx

 * @device: Pointer to the device structure

 * @adreno_dev: Pointer to the device structure

 * Performs register writes to enable protected access to sensitive

 * registers

 */

static void a4xx_protect_init(struct kgsl_device *device)

static void a4xx_protect_init(struct adreno_device *adreno_dev)

{

	struct kgsl_device *device = &adreno_dev->dev;

	int index = 0;

	struct kgsl_protected_registers *iommu_regs;



	/* enable access protection to privileged registers */

	kgsl_regwrite(device, A4XX_CP_PROTECT_CTRL, 0x00000007);

	/* RBBM registers */

	adreno_set_protected_registers(device, &index, 0x4, 2);

	adreno_set_protected_registers(device, &index, 0x8, 3);

	adreno_set_protected_registers(device, &index, 0x10, 4);

	adreno_set_protected_registers(device, &index, 0x20, 5);

	adreno_set_protected_registers(device, &index, 0x40, 6);

	adreno_set_protected_registers(device, &index, 0x80, 4);

	adreno_set_protected_registers(adreno_dev, &index, 0x4, 2);

	adreno_set_protected_registers(adreno_dev, &index, 0x8, 3);

	adreno_set_protected_registers(adreno_dev, &index, 0x10, 4);

	adreno_set_protected_registers(adreno_dev, &index, 0x20, 5);

	adreno_set_protected_registers(adreno_dev, &index, 0x40, 6);

	adreno_set_protected_registers(adreno_dev, &index, 0x80, 4);



	/* Content protection registers */

	if (kgsl_mmu_is_secured(&device->mmu)) {

		adreno_set_protected_registers(device, &index,

		adreno_set_protected_registers(adreno_dev, &index,

			   A4XX_RBBM_SECVID_TSB_TRUSTED_BASE, 3);

		adreno_set_protected_registers(device, &index,

		adreno_set_protected_registers(adreno_dev, &index,

			   A4XX_RBBM_SECVID_TRUST_CONTROL, 1);

	}



	/* CP registers */

	adreno_set_protected_registers(device, &index, 0x200, 7);

	adreno_set_protected_registers(device, &index, 0x580, 4);

	adreno_set_protected_registers(adreno_dev, &index, 0x200, 7);

	adreno_set_protected_registers(adreno_dev, &index, 0x580, 4);



	/* RB registers */

	adreno_set_protected_registers(device, &index, 0xCC0, 0);

	adreno_set_protected_registers(adreno_dev, &index, 0xCC0, 0);



	/* HLSQ registers */

	adreno_set_protected_registers(device, &index, 0xE00, 0);

	adreno_set_protected_registers(adreno_dev, &index, 0xE00, 0);



	/* VPC registers */

	adreno_set_protected_registers(device, &index, 0xE60, 1);

	adreno_set_protected_registers(adreno_dev, &index, 0xE60, 1);



	/* SMMU registers */

	iommu_regs = kgsl_mmu_get_prot_regs(&device->mmu);

	if (iommu_regs)

		adreno_set_protected_registers(device, &index,

		adreno_set_protected_registers(adreno_dev, &index,

				iommu_regs->base, iommu_regs->range);

}
@@ -545,7 +546,7 @@ static void a4xx_start(struct adreno_device *adreno_dev) 
{

	struct kgsl_device *device = &adreno_dev->dev;



	adreno_vbif_start(device, a4xx_vbif_platforms,

	adreno_vbif_start(adreno_dev, a4xx_vbif_platforms,

			ARRAY_SIZE(a4xx_vbif_platforms));

	/* Make all blocks contribute to the GPU BUSY perf counter */

	kgsl_regwrite(device, A4XX_RBBM_GPU_BUSY_MASKED, 0xFFFFFFFF);
@@ -615,7 +616,7 @@ static void a4xx_start(struct adreno_device *adreno_dev) 
		kgsl_regwrite(device, A4XX_RBBM_CLOCK_DELAY_HLSQ, val);

	}



	a4xx_protect_init(device);

	a4xx_protect_init(adreno_dev);

}



int a4xx_perfcounter_enable_vbif(struct adreno_device *adreno_dev,

drivers/gpu/msm/adreno_coresight.c

+4 −3
Original line number Diff line number Diff line
@@ -278,8 +278,9 @@ static const struct coresight_ops adreno_coresight_ops = { 
	.source_ops = &adreno_coresight_source_ops,

};



void adreno_coresight_remove(struct kgsl_device *device)

void adreno_coresight_remove(struct adreno_device *adreno_dev)

{

	struct kgsl_device *device = &adreno_dev->dev;

	struct kgsl_device_platform_data *pdata =

		dev_get_platdata(&device->pdev->dev);
@@ -287,11 +288,11 @@ void adreno_coresight_remove(struct kgsl_device *device) 
	pdata->csdev = NULL;

}



int adreno_coresight_init(struct kgsl_device *device)

int adreno_coresight_init(struct adreno_device *adreno_dev)

{

	int ret = 0;

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	struct kgsl_device *device = &adreno_dev->dev;

	struct kgsl_device_platform_data *pdata =

		dev_get_platdata(&device->pdev->dev);

	struct coresight_desc desc;