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Commit 3d7aa609 authored by Vikram Mulukutla's avatar Vikram Mulukutla
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qcom: clock-cpu-8994: Fix configuration for V1 



The function that configures the A57 clocks before
probe() initializes A57 PLL1. Do not initialize the
A57 PLL1 again.

Change-Id: I1f037c4018ad58250d03b9ba96205621db3cd656
Signed-off-by: default avatarVikram Mulukutla <markivx@codeaurora.org>
parent 515aa59c

drivers/clk/qcom/clock-cpu-8994.c

+2 −12
Original line number Original line Diff line number Diff line
@@ -871,31 +871,21 @@ static void perform_v1_fixup(void) 
	 * 3. Configure the PLL to generate 1.5936 GHz.

	 * 3. Configure the PLL to generate 1.5936 GHz.

	 */

	 */

	a53_pll1.c.ops->disable(&a53_pll1.c);

	a53_pll1.c.ops->disable(&a53_pll1.c);

	a57_pll1.c.ops->disable(&a57_pll1.c);





	/* Set the divider on the PLL1 input to the A53 LF MUX (div 2) */

	/* Set the divider on the PLL1 input to the A53 LF MUX (div 2) */

	regval = readl_relaxed(vbases[ALIAS0_GLB_BASE] + MUX_OFFSET);

	regval = readl_relaxed(vbases[ALIAS0_GLB_BASE] + MUX_OFFSET);

	regval |= BIT(6);

	regval |= BIT(6);

	writel_relaxed(regval, vbases[ALIAS0_GLB_BASE] + MUX_OFFSET);

	writel_relaxed(regval, vbases[ALIAS0_GLB_BASE] + MUX_OFFSET);





	/* Set the divider on the PLL1 input to the A57 LF MUX (div 2) */

	regval = readl_relaxed(vbases[ALIAS1_GLB_BASE] + MUX_OFFSET);

	regval |= BIT(6);

	writel_relaxed(regval, vbases[ALIAS1_GLB_BASE] + MUX_OFFSET);



	a53_pll1.c.ops->set_rate(&a53_pll1.c, 1593600000);

	a53_pll1.c.ops->set_rate(&a53_pll1.c, 1593600000);

	a57_pll1.c.ops->set_rate(&a57_pll1.c, 1593600000);





	a53_pll1.c.rate = 1593600000;

	a53_pll1.c.rate = 1593600000;

	a57_pll1.c.rate = 1593600000;





	/* Enable the A53 and A57 secondary PLLs */

	/* Enable the A53 secondary PLL */

	a53_pll1.c.ops->enable(&a53_pll1.c);

	a53_pll1.c.ops->enable(&a53_pll1.c);

	a57_pll1.c.ops->enable(&a57_pll1.c);





	/* Select the "safe" parent on the secondary muxes */

	/* Select the "safe" parent on the secondary mux */

	__cpu_mux_set_sel(&a53_lf_mux, 1);

	__cpu_mux_set_sel(&a53_lf_mux, 1);

	__cpu_mux_set_sel(&a57_lf_mux, 1);

}

}





static int cpu_clock_8994_driver_probe(struct platform_device *pdev)

static int cpu_clock_8994_driver_probe(struct platform_device *pdev)