clk: qcom: clock-cpu-8994: Do not modify the A53/A57 clock tree divider

The divider that lies between the A53/A57 HF and LF muxes is not
glitch free. Do not modify it during normal operation. The following
description states how this is to be achieved for each cluster.

For the A53s, this is achieved by:
1. Using the post-divider in the PLLs to achieve the
   division necessary to generate frequencies < 600Mhz.
2. Fixing the CDIV to div-1 during boot. Bootchain is
   guaranteed to never program it to div-2.
3. Removing the clock switch during power collapse.
4. Enabling hardware/RPM control of the PLLs (RPM
   turns any running CPU PLL off before deep sleep).

For the A57s, this is achieved by:
1. Fixing the CDIV to div-1 during boot.
2. Removing all frequencies below 600MHz for the A57s
   This implies the divider never needs to be set
   to div-2
3. The power-collapse frequency is 600Mhz instead of
   300Mhz.

The 300Mhz rate can no longer be generated for either
A53 or A57, but userspace was never using it as a
DCVS performance level anyway.

Change-Id: Ife2378b6b716965734ea8fd898f3558426ffcff2
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>