Loading drivers/pci/host/pci-msm.c +5 −0 Original line number Diff line number Diff line Loading @@ -161,6 +161,7 @@ #define PCIE20_PARF_PHY_REFCLK 0x4C #define PCIE20_PARF_CONFIG_BITS 0x50 #define PCIE20_PARF_DBI_BASE_ADDR 0x168 #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178 #define PCIE20_PARF_LTSSM 0x1B0 Loading Loading @@ -1772,6 +1773,10 @@ int msm_pcie_enable(struct msm_pcie_dev_t *dev, u32 options) writel_relaxed(0x3656, dev->parf + PCIE20_PARF_SYS_CTRL); if (dev->dev_mem_res->end - dev->dev_mem_res->start > SZ_8M) writel_relaxed(SZ_16M, dev->parf + PCIE20_PARF_SLV_ADDR_SPACE_SIZE); if (dev->use_msi) { PCIE_DBG(dev, "RC%d: enable WR halt.\n", dev->rc_idx); msm_pcie_write_mask(dev->parf + Loading Loading
drivers/pci/host/pci-msm.c +5 −0 Original line number Diff line number Diff line Loading @@ -161,6 +161,7 @@ #define PCIE20_PARF_PHY_REFCLK 0x4C #define PCIE20_PARF_CONFIG_BITS 0x50 #define PCIE20_PARF_DBI_BASE_ADDR 0x168 #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178 #define PCIE20_PARF_LTSSM 0x1B0 Loading Loading @@ -1772,6 +1773,10 @@ int msm_pcie_enable(struct msm_pcie_dev_t *dev, u32 options) writel_relaxed(0x3656, dev->parf + PCIE20_PARF_SYS_CTRL); if (dev->dev_mem_res->end - dev->dev_mem_res->start > SZ_8M) writel_relaxed(SZ_16M, dev->parf + PCIE20_PARF_SLV_ADDR_SPACE_SIZE); if (dev->use_msi) { PCIE_DBG(dev, "RC%d: enable WR halt.\n", dev->rc_idx); msm_pcie_write_mask(dev->parf + Loading