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Commit 3a0e342d authored by Patrick Daly's avatar Patrick Daly Committed by Stephen Boyd
Browse files

msm: clock-8960: Add support for msm8960ab clocks 



Apply differences between 8960 and 8960ab, including:
1) Set PLL3 frequency to 650MHz.

2) Update frequency table and FMAX_HIGH/NOMINAL/LOW for mdp_clk,
gfx3d_clk.

3) Update reg_init, 8960_pre_init, 8960_post_init register settings.
Remove all bits marked "reserved" in 8960ab.

4) Separate lookup table into 8960 common clocks, 8960ab only clocks,
and 8960-only clocks.

Change-Id: Ie0fde5c0a289c70005622d61079ed3cddeeae095
Signed-off-by: default avatarPatrick Daly <pdaly@codeaurora.org>
parent c8bdfb50

arch/arm/mach-msm/clock-8960.c

+122 −31
Original line number Diff line number Diff line
@@ -194,6 +194,7 @@ 
#define DSI2_ESC_CC_REG				REG_MM(0x013C)

#define DSI_PIXEL_CC_REG			REG_MM(0x0130)

#define DSI2_PIXEL_CC_REG			REG_MM(0x0094)

#define DSI2_PIXEL_CC2_REG			REG_MM(0x0264)

#define DBG_BUS_VEC_A_REG			REG_MM(0x01C8)

#define DBG_BUS_VEC_B_REG			REG_MM(0x01CC)

#define DBG_BUS_VEC_C_REG			REG_MM(0x01D0)
@@ -785,7 +786,7 @@ static struct branch_clk vcap_axi_clk = { 
};



/* gfx3d_axi_clk is set as a dependency of gmem_axi_clk at runtime */

static struct branch_clk gfx3d_axi_clk_8064 = {

static struct branch_clk gfx3d_axi_clk = {

	.b = {

		.ctl_reg = MAXI_EN5_REG,

		.en_mask = BIT(25),
@@ -799,7 +800,7 @@ static struct branch_clk gfx3d_axi_clk_8064 = { 
	.c = {

		.dbg_name = "gfx3d_axi_clk",

		.ops = &clk_ops_branch,

		CLK_INIT(gfx3d_axi_clk_8064.c),

		CLK_INIT(gfx3d_axi_clk.c),

	},

};
@@ -3406,6 +3407,27 @@ static struct rcg_clk gfx2d1_clk = { 
		.ctl_val = CC_BANKED(9, 6, n), \

	}



static struct clk_freq_tbl clk_tbl_gfx3d_8960ab[] = {

	F_GFX3D(        0, gnd,  0,  0),

	F_GFX3D( 27000000, pxo,  0,  0),

	F_GFX3D( 48000000, pll8, 1,  8),

	F_GFX3D( 54857000, pll8, 1,  7),

	F_GFX3D( 64000000, pll8, 1,  6),

	F_GFX3D( 76800000, pll8, 1,  5),

	F_GFX3D( 96000000, pll8, 1,  4),

	F_GFX3D(128000000, pll8, 1,  3),

	F_GFX3D(145455000, pll2, 2, 11),

	F_GFX3D(160000000, pll2, 1,  5),

	F_GFX3D(177778000, pll2, 2,  9),

	F_GFX3D(200000000, pll2, 1,  4),

	F_GFX3D(228571000, pll2, 2,  7),

	F_GFX3D(266667000, pll2, 1,  3),

	F_GFX3D(320000000, pll2, 2,  5),

	F_GFX3D(325000000, pll3, 1,  2),

	F_GFX3D(400000000, pll2, 1,  2),

	F_END

};



static struct clk_freq_tbl clk_tbl_gfx3d_8960[] = {

	F_GFX3D(        0, gnd,  0,  0),

	F_GFX3D( 27000000, pxo,  0,  0),
@@ -3713,6 +3735,27 @@ static struct rcg_clk jpegd_clk = { 
		.ns_val = NS_MND_BANKED8(22, 14, n, m, 3, 0, s##_to_mm_mux), \

		.ctl_val = CC_BANKED(9, 6, n), \

	}

static struct clk_freq_tbl clk_tbl_mdp_8960ab[] = {

	F_MDP(        0, gnd,  0,  0),

	F_MDP(  9600000, pll8, 1, 40),

	F_MDP( 13710000, pll8, 1, 28),

	F_MDP( 27000000, pxo,  0,  0),

	F_MDP( 29540000, pll8, 1, 13),

	F_MDP( 34910000, pll8, 1, 11),

	F_MDP( 38400000, pll8, 1, 10),

	F_MDP( 59080000, pll8, 2, 13),

	F_MDP( 76800000, pll8, 1,  5),

	F_MDP( 85330000, pll8, 2,  9),

	F_MDP( 96000000, pll8, 1,  4),

	F_MDP(128000000, pll8, 1,  3),

	F_MDP(160000000, pll2, 1,  5),

	F_MDP(177780000, pll2, 2,  9),

	F_MDP(200000000, pll2, 1,  4),

	F_MDP(228571000, pll2, 2,  7),

	F_MDP(266667000, pll2, 1,  3),

	F_END

};



static struct clk_freq_tbl clk_tbl_mdp[] = {

	F_MDP(        0, gnd,  0,  0),

	F_MDP(  9600000, pll8, 1, 40),
@@ -4853,7 +4896,7 @@ static struct measure_sel measure_mux[] = { 
	{ TEST_MM_HS(0x35), &vcap_axi_clk.c },

	{ TEST_MM_HS(0x36), &rgb_tv_clk.c },

	{ TEST_MM_HS(0x37), &npl_tv_clk.c },

	{ TEST_MM_HS(0x38), &gfx3d_axi_clk_8064.c },

	{ TEST_MM_HS(0x38), &gfx3d_axi_clk.c },



	{ TEST_LPA(0x0F), &mi2s_bit_clk.c },

	{ TEST_LPA(0x10), &codec_i2s_mic_bit_clk.c },
@@ -5231,7 +5274,7 @@ static struct clk_lookup msm_clocks_8064[] = { 
	CLK_LOOKUP("core_clk",		gfx3d_clk.c,	"kgsl-3d0.0"),

	CLK_LOOKUP("core_clk",		gfx3d_clk.c,	"footswitch-8x60.2"),

	CLK_LOOKUP("bus_clk",

			    gfx3d_axi_clk_8064.c, "footswitch-8x60.2"),

			    gfx3d_axi_clk.c, "footswitch-8x60.2"),

	CLK_LOOKUP("iface_clk",         vcap_p_clk.c,           ""),

	CLK_LOOKUP("iface_clk",         vcap_p_clk.c,           "msm_vcap.0"),

	CLK_LOOKUP("iface_clk",         vcap_p_clk.c,	"footswitch-8x60.10"),
@@ -5337,7 +5380,7 @@ static struct clk_lookup msm_clocks_8064[] = { 
	CLK_LOOKUP("core_clk",		vfe_axi_clk.c,		""),

	CLK_LOOKUP("core_clk",		vcodec_axi_a_clk.c,	""),

	CLK_LOOKUP("core_clk",		vcodec_axi_b_clk.c,	""),

	CLK_LOOKUP("core_clk",		gfx3d_axi_clk_8064.c,	""),

	CLK_LOOKUP("core_clk",		gfx3d_axi_clk.c,	""),



	CLK_LOOKUP("dfab_dsps_clk",	dfab_dsps_clk.c, NULL),

	CLK_LOOKUP("core_clk",		dfab_usb_hs_clk.c,	"msm_otg"),
@@ -5367,8 +5410,9 @@ static struct clk_lookup msm_clocks_8064[] = { 
	CLK_LOOKUP("core_clk",		vfe_axi_clk.c,		"msm_iommu.6"),

	CLK_LOOKUP("core_clk",		vcodec_axi_a_clk.c,	"msm_iommu.7"),

	CLK_LOOKUP("core_clk",		vcodec_axi_b_clk.c,	"msm_iommu.8"),

	CLK_LOOKUP("core_clk",		gfx3d_axi_clk_8064.c,	"msm_iommu.9"),

	CLK_LOOKUP("core_clk",		gfx3d_axi_clk_8064.c,	"msm_iommu.10"),

	CLK_LOOKUP("core_clk",		gfx3d_axi_clk.c,	"msm_iommu.9"),

	CLK_LOOKUP("core_clk",		gfx3d_axi_clk.c,	"msm_iommu.10"),



	CLK_LOOKUP("core_clk",		vcap_axi_clk.c,		"msm_iommu.11"),



	CLK_LOOKUP("mdp_iommu_clk", mdp_axi_clk.c,	"msm_vidc.0"),
@@ -5390,7 +5434,7 @@ static struct clk_lookup msm_clocks_8064[] = { 
	CLK_LOOKUP("krait3_mclk",	krait3_m_clk, ""),

};



static struct clk_lookup msm_clocks_8960[] = {

static struct clk_lookup msm_clocks_8960_common[] __initdata = {

	CLK_LOOKUP("xo",		cxo_a_clk.c,	""),

	CLK_LOOKUP("xo",		pxo_a_clk.c,	""),

	CLK_LOOKUP("cxo",		cxo_clk.c,	"wcnss_wlan.0"),
@@ -5569,10 +5613,6 @@ static struct clk_lookup msm_clocks_8960[] = { 
	CLK_LOOKUP("byte_clk",	dsi2_byte_clk.c,	"mipi_dsi.2"),

	CLK_LOOKUP("esc_clk",	dsi1_esc_clk.c,		"mipi_dsi.1"),

	CLK_LOOKUP("esc_clk",	dsi2_esc_clk.c,		"mipi_dsi.2"),

	CLK_LOOKUP("core_clk",		gfx2d0_clk.c,	"kgsl-2d0.0"),

	CLK_LOOKUP("core_clk",		gfx2d0_clk.c,	"footswitch-8x60.0"),

	CLK_LOOKUP("core_clk",		gfx2d1_clk.c,	"kgsl-2d1.1"),

	CLK_LOOKUP("core_clk",		gfx2d1_clk.c,	"footswitch-8x60.1"),

	CLK_LOOKUP("core_clk",		gfx3d_clk.c,	"kgsl-3d0.0"),

	CLK_LOOKUP("core_clk",		gfx3d_clk.c,	"footswitch-8x60.2"),

	CLK_LOOKUP("bus_clk",		ijpeg_axi_clk.c, "footswitch-8x60.3"),
@@ -5592,8 +5632,6 @@ static struct clk_lookup msm_clocks_8960[] = { 
	CLK_LOOKUP("src_clk",	tv_src_clk.c,		"dtv.0"),

	CLK_LOOKUP("src_clk",	tv_src_clk.c,		"tvenc.0"),

	CLK_LOOKUP("tv_src_clk",	tv_src_clk.c,	"footswitch-8x60.4"),

	CLK_LOOKUP("enc_clk",	tv_enc_clk.c,		"tvenc.0"),

	CLK_LOOKUP("dac_clk",	tv_dac_clk.c,		"tvenc.0"),

	CLK_LOOKUP("core_clk",		vcodec_clk.c,	"msm_vidc.0"),

	CLK_LOOKUP("core_clk",		vcodec_clk.c,	"footswitch-8x60.7"),

	CLK_LOOKUP("mdp_clk",	mdp_tv_clk.c,		"dtv.0"),
@@ -5622,10 +5660,6 @@ static struct clk_lookup msm_clocks_8960[] = { 
	CLK_LOOKUP("slave_iface_clk",	dsi1_s_p_clk.c,		"mipi_dsi.1"),

	CLK_LOOKUP("master_iface_clk",	dsi2_m_p_clk.c,		"mipi_dsi.2"),

	CLK_LOOKUP("slave_iface_clk",	dsi2_s_p_clk.c,		"mipi_dsi.2"),

	CLK_LOOKUP("iface_clk",		gfx2d0_p_clk.c,	"kgsl-2d0.0"),

	CLK_LOOKUP("iface_clk",		gfx2d0_p_clk.c,	"footswitch-8x60.0"),

	CLK_LOOKUP("iface_clk",		gfx2d1_p_clk.c,	"kgsl-2d1.1"),

	CLK_LOOKUP("iface_clk",		gfx2d1_p_clk.c,	"footswitch-8x60.1"),

	CLK_LOOKUP("iface_clk",		gfx3d_p_clk.c,	"kgsl-3d0.0"),

	CLK_LOOKUP("iface_clk",		gfx3d_p_clk.c,	"footswitch-8x60.2"),

	CLK_LOOKUP("master_iface_clk",	hdmi_m_p_clk.c,	"hdmi_msm.1"),
@@ -5639,7 +5673,6 @@ static struct clk_lookup msm_clocks_8960[] = { 
	CLK_LOOKUP("iface_clk",		smmu_p_clk.c,	"msm_iommu"),

	CLK_LOOKUP("iface_clk",		rot_p_clk.c,	"msm_rotator.0"),

	CLK_LOOKUP("iface_clk",		rot_p_clk.c,	"footswitch-8x60.6"),

	CLK_LOOKUP("iface_clk",	tv_enc_p_clk.c,		"tvenc.0"),

	CLK_LOOKUP("iface_clk",		vcodec_p_clk.c,	"msm_vidc.0"),

	CLK_LOOKUP("iface_clk",		vcodec_p_clk.c,	"footswitch-8x60.7"),

	CLK_LOOKUP("vfe_pclk",		vfe_p_clk.c,		"msm_vfe.0"),
@@ -5680,8 +5713,6 @@ static struct clk_lookup msm_clocks_8960[] = { 
	CLK_LOOKUP("core_clk",		vcodec_axi_a_clk.c,	"msm_iommu.7"),

	CLK_LOOKUP("core_clk",		vcodec_axi_b_clk.c,	"msm_iommu.8"),

	CLK_LOOKUP("core_clk",		gfx3d_clk.c,		"msm_iommu.9"),

	CLK_LOOKUP("core_clk",		gfx2d0_clk.c,		"msm_iommu.10"),

	CLK_LOOKUP("core_clk",		gfx2d1_clk.c,		"msm_iommu.11"),



	CLK_LOOKUP("mdp_iommu_clk", mdp_axi_clk.c,	"msm_vidc.0"),

	CLK_LOOKUP("rot_iommu_clk",	rot_axi_clk.c,	"msm_vidc.0"),
@@ -5715,6 +5746,32 @@ static struct clk_lookup msm_clocks_8960[] = { 
	CLK_LOOKUP("q6_func_clk",	q6_func_clk,  ""),

};



static struct clk_lookup msm_clocks_8960_only[] __initdata = {

	CLK_LOOKUP("enc_clk",	tv_enc_clk.c,		"tvenc.0"),

	CLK_LOOKUP("dac_clk",	tv_dac_clk.c,		"tvenc.0"),

	CLK_LOOKUP("iface_clk",	tv_enc_p_clk.c,		"tvenc.0"),



	CLK_LOOKUP("core_clk",		gfx2d0_clk.c,	"kgsl-2d0.0"),

	CLK_LOOKUP("core_clk",		gfx2d0_clk.c,	"footswitch-8x60.0"),

	CLK_LOOKUP("core_clk",		gfx2d1_clk.c,	"kgsl-2d1.1"),

	CLK_LOOKUP("core_clk",		gfx2d1_clk.c,	"footswitch-8x60.1"),

	CLK_LOOKUP("iface_clk",		gfx2d0_p_clk.c,	"kgsl-2d0.0"),

	CLK_LOOKUP("iface_clk",		gfx2d0_p_clk.c,	"footswitch-8x60.0"),

	CLK_LOOKUP("iface_clk",		gfx2d1_p_clk.c,	"kgsl-2d1.1"),

	CLK_LOOKUP("iface_clk",		gfx2d1_p_clk.c,	"footswitch-8x60.1"),

	CLK_LOOKUP("core_clk",		gfx2d0_clk.c,		"msm_iommu.10"),

	CLK_LOOKUP("core_clk",		gfx2d1_clk.c,		"msm_iommu.11"),

};



static struct clk_lookup msm_clocks_8960ab_only[] __initdata = {

	CLK_LOOKUP("bus_clk", gfx3d_axi_clk.c, "footswitch-8x60.2"),

	CLK_LOOKUP("div_clk",	tv_src_div_clk.c,	""),

};



static struct clk_lookup msm_clocks_8960[ARRAY_SIZE(msm_clocks_8960_common)

	+ ARRAY_SIZE(msm_clocks_8960_only)

	+ ARRAY_SIZE(msm_clocks_8960ab_only)];



static struct clk_lookup msm_clocks_8930[] = {

	CLK_LOOKUP("xo",		cxo_clk.c,	"msm_xo"),

	CLK_LOOKUP("cxo",		cxo_clk.c,	"wcnss_wlan.0"),
@@ -6112,12 +6169,12 @@ static void __init reg_init(void) 
	 */

	/*

	 * Initialize MM AHB registers: Enable the FPB clock and disable HW

	 * gating on 8627 for all clocks. Also set VFE_AHB's

	 * gating on 8627 and 8960 for all clocks. Also set VFE_AHB's

	 * FORCE_CORE_ON bit to prevent its memory from being collapsed when

	 * the clock is halted. The sleep and wake-up delays are set to safe

	 * values.

	 */

	if (cpu_is_msm8627()) {

	if (cpu_is_msm8627() || cpu_is_msm8960ab()) {

		rmwreg(0x00000003, AHB_EN_REG,  0x6C000103);

		writel_relaxed(0x000007F9, AHB_EN2_REG);

	} else {
@@ -6135,7 +6192,7 @@ static void __init reg_init(void) 
	/* Initialize MM AXI registers: Enable HW gating for all clocks that

	 * support it. Also set FORCE_CORE_ON bits, and any sleep and wake-up

	 * delays to safe values. */

	if ((cpu_is_msm8960() &&

	if (cpu_is_msm8960ab() || (cpu_is_msm8960() &&

			SOCINFO_VERSION_MAJOR(socinfo_get_version()) < 3) ||

			cpu_is_msm8627()) {

		rmwreg(0x000007F9, MAXI_EN_REG,  0x0803FFFF);
@@ -6152,8 +6209,13 @@ static void __init reg_init(void) 
		rmwreg(0x019FECFF, MAXI_EN5_REG, 0x01FFEFFF);

	if (cpu_is_msm8930() || cpu_is_msm8930aa() || cpu_is_msm8627())

		rmwreg(0x000004FF, MAXI_EN5_REG, 0x00000FFF);

	if (cpu_is_msm8960ab())

		rmwreg(0x009FE000, MAXI_EN5_REG, 0x01FFE000);



	if (cpu_is_msm8627())

		rmwreg(0x000003C7, SAXI_EN_REG,  0x00003FFF);

	else if (cpu_is_msm8960ab())

		rmwreg(0x000001C6, SAXI_EN_REG,  0x00001DF6);

	else

		rmwreg(0x00003C38, SAXI_EN_REG,  0x00003FFF);
@@ -6181,14 +6243,19 @@ static void __init reg_init(void) 
	rmwreg(0x80FF0000, VFE_CC_REG,        0xE0FF4010);

	rmwreg(0x800000FF, VFE_CC2_REG,       0xE00000FF);

	rmwreg(0x80FF0000, VPE_CC_REG,        0xE0FF0010);

	if (cpu_is_msm8960() || cpu_is_apq8064()) {

	if (cpu_is_msm8960ab() || cpu_is_msm8960() || cpu_is_apq8064()) {

		rmwreg(0x80FF0000, DSI2_BYTE_CC_REG,  0xE0FF0010);

		rmwreg(0x80FF0000, DSI2_PIXEL_CC_REG, 0xE0FF0010);

		rmwreg(0x80FF0000, JPEGD_CC_REG,      0xE0FF0010);

	}

	if (cpu_is_msm8960ab())

		rmwreg(0x00000001, DSI2_PIXEL_CC2_REG, 0x00000001);



	if (cpu_is_msm8960() || cpu_is_msm8930() || cpu_is_msm8930aa() ||

	    cpu_is_msm8627())

		rmwreg(0x80FF0000, TV_CC_REG,        0xE1FFC010);

	if (cpu_is_msm8960ab())

		rmwreg(0x00000000, TV_CC_REG,        0x00004010);



	if (cpu_is_msm8960()) {

		rmwreg(0x80FF0000, GFX2D0_CC_REG,     0xE0FF0010);
@@ -6222,12 +6289,12 @@ static void __init reg_init(void) 
	writel_relaxed(BIT(15), PDM_CLK_NS_REG);



	/* Source SLIMBus xo src from slimbus reference clock */

	if (cpu_is_msm8960())

	if (cpu_is_msm8960ab() || cpu_is_msm8960())

		writel_relaxed(0x3, SLIMBUS_XO_SRC_CLK_CTL_REG);



	/* Source the dsi_byte_clks from the DSI PHY PLLs */

	rmwreg(0x1, DSI1_BYTE_NS_REG, 0x7);

	if (cpu_is_msm8960() || cpu_is_apq8064())

	if (cpu_is_msm8960ab() || cpu_is_msm8960() || cpu_is_apq8064())

		rmwreg(0x2, DSI2_BYTE_NS_REG, 0x7);



	/* Source the dsi1_esc_clk from the DSI1 PHY PLLs */
@@ -6289,6 +6356,7 @@ static void __init reg_init(void) 
	}

}



struct clock_init_data msm8960_clock_init_data __initdata;

static void __init msm8960_clock_pre_init(void)

{

	/* Initialize clock registers. */
@@ -6313,6 +6381,29 @@ static void __init msm8960_clock_pre_init(void) 
		pcm_clk.freq_tbl = clk_tbl_pcm_492;

	}



	if (cpu_is_msm8960() || cpu_is_msm8960ab())

		memcpy(msm_clocks_8960, msm_clocks_8960_common,

			sizeof(msm_clocks_8960_common));

	if (cpu_is_msm8960ab()) {

		pll3_clk.c.rate = 650000000;

		gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8960ab;

		gfx3d_clk.c.fmax[VDD_DIG_LOW] = 192000000;

		gfx3d_clk.c.fmax[VDD_DIG_NOMINAL] = 325000000;

		gfx3d_clk.c.fmax[VDD_DIG_HIGH] = 400000000;

		mdp_clk.freq_tbl = clk_tbl_mdp_8960ab;

		mdp_clk.c.fmax[VDD_DIG_LOW] = 128000000;

		mdp_clk.c.fmax[VDD_DIG_NOMINAL] = 266667000;



		memcpy(msm_clocks_8960 + ARRAY_SIZE(msm_clocks_8960_common),

			msm_clocks_8960ab_only, sizeof(msm_clocks_8960ab_only));

		msm8960_clock_init_data.size -=

			ARRAY_SIZE(msm_clocks_8960_only);

	} else if (cpu_is_msm8960()) {

		memcpy(msm_clocks_8960 + ARRAY_SIZE(msm_clocks_8960_common),

			 msm_clocks_8960_only, sizeof(msm_clocks_8960_only));

		msm8960_clock_init_data.size -=

			ARRAY_SIZE(msm_clocks_8960ab_only);

	}

	/*

	 * Change the freq tables for and voltage requirements for

	 * clocks which differ between 8960 and 8064.
@@ -6331,7 +6422,7 @@ static void __init msm8960_clock_pre_init(void) 
		memcpy(vfe_clk.c.fmax, fmax_vfe_8064,

		       sizeof(vfe_clk.c.fmax));



		gmem_axi_clk.c.depends = &gfx3d_axi_clk_8064.c;

		gmem_axi_clk.c.depends = &gfx3d_axi_clk.c;

	}



	/*
@@ -6380,8 +6471,8 @@ static void __init msm8960_clock_post_init(void) 
		clk_set_rate(&usb_hs4_xcvr_clk.c, 60000000);

	}

	clk_set_rate(&usb_fs1_src_clk.c, 60000000);

	if (cpu_is_msm8960() || cpu_is_msm8930() || cpu_is_msm8930aa() ||

	    cpu_is_msm8627())

	if (cpu_is_msm8960ab() || cpu_is_msm8960() || cpu_is_msm8930() ||

		cpu_is_msm8930aa() || cpu_is_msm8627())

		clk_set_rate(&usb_fs2_src_clk.c, 60000000);

	clk_set_rate(&usb_hsic_xcvr_fs_clk.c, 60000000);

	clk_set_rate(&usb_hsic_hsic_src_clk.c, 480000000);