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Commit 397fe157 authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm: extract drm_dp_max_lane_count helper 



Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Acked-by: default avatarDave Airlie <airlied@gmail.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 3b5c662e

drivers/gpu/drm/i915/intel_dp.c

+2 −15
Original line number Diff line number Diff line
@@ -124,19 +124,6 @@ intel_edp_target_clock(struct intel_encoder *intel_encoder, 
		return mode->clock;

}



static int

intel_dp_max_lane_count(struct intel_dp *intel_dp)

{

	int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;

	switch (max_lane_count) {

	case 1: case 2: case 4:

		break;

	default:

		max_lane_count = 4;

	}

	return max_lane_count;

}



static int

intel_dp_max_link_bw(struct intel_dp *intel_dp)

{
@@ -197,7 +184,7 @@ intel_dp_adjust_dithering(struct intel_dp *intel_dp, 
			  bool adjust_mode)

{

	int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));

	int max_lanes = intel_dp_max_lane_count(intel_dp);

	int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);

	int max_rate, mode_rate;



	mode_rate = intel_dp_link_required(mode->clock, 24);
@@ -699,7 +686,7 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, 
	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

	struct intel_connector *intel_connector = intel_dp->attached_connector;

	int lane_count, clock;

	int max_lane_count = intel_dp_max_lane_count(intel_dp);

	int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);

	int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;

	int bpp, mode_rate;

	static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };

drivers/gpu/drm/radeon/atombios_dp.c

+1 −6
Original line number Diff line number Diff line
@@ -347,11 +347,6 @@ static int dp_get_max_dp_pix_clock(int link_rate, 
	return (link_rate * lane_num * 8) / bpp;

}



static u8 dp_get_max_lane_number(u8 dpcd[DP_DPCD_SIZE])

{

	return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;

}



/***** radeon specific DP functions *****/



/* First get the min lane# when low rate is used according to pixel clock
@@ -364,7 +359,7 @@ static int radeon_dp_get_dp_lane_number(struct drm_connector *connector, 
{

	int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));

	int max_link_rate = drm_dp_max_link_rate(dpcd);

	int max_lane_num = dp_get_max_lane_number(dpcd);

	int max_lane_num = drm_dp_max_lane_count(dpcd);

	int lane_num;

	int max_dp_pix_clock;

include/drm/drm_dp_helper.h

+7 −0
Original line number Diff line number Diff line
@@ -346,4 +346,11 @@ drm_dp_max_link_rate(u8 dpcd[DP_RECEIVER_CAP_SIZE]) 
{

	return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);

}



static inline u8

drm_dp_max_lane_count(u8 dpcd[DP_RECEIVER_CAP_SIZE])

{

	return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;

}



#endif /* _DRM_DP_HELPER_H_ */