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Commit 3901e721 authored by Venkat Devarasetty's avatar Venkat Devarasetty
Browse files

msm: pm: Correct the bit checking for cache type 



For ARM v7 the cache size ID register bit 30 indicates
if write back is supported. Currently bit 31 is checked which
is incorrect.

Change-Id: Ic52bbd4f8d9d58468972b9db8539b241ed982712
Signed-off-by: default avatarVenkat Devarasetty <vdevaras@codeaurora.org>
parent d81481d4

drivers/power/qcom/msm-pm.c

+2 −2
Original line number Diff line number Diff line
@@ -96,7 +96,7 @@ static inline void msm_arch_idle(void) 


static bool msm_pm_is_L1_writeback(void)

{

	u32 cache_id;

	u32 cache_id = 0;



#if defined(CONFIG_CPU_V7)

	u32 sel = 0;
@@ -106,7 +106,7 @@ static bool msm_pm_is_L1_writeback(void) 
		      :[ccsidr]"=r" (cache_id)

		      :[ccselr]"r" (sel)

		     );

	return cache_id & BIT(31);

	return cache_id & BIT(30);

#elif defined(CONFIG_ARM64)

	u32 sel = 0;

	asm volatile("msr csselr_el1, %[ccselr]\n\t"