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Commit 36318d7a authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "msm: remove code, dts, and references to MSM9625"

parents 2bf81e84 c37b3a40

Documentation/devicetree/bindings/arm/msm/acpuclock/acpuclock-9625.txt

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* Qualcomm Application CPU clock driver



acpuclock-9625 is the application cpu clock driver for MDM9625. It is used for

cpu frequency scaling, voltage scaling and bus bandwidth scaling.



Required properties:

- compatible: "qcom,acpuclk-9625"

- reg: offset and length of the register sets for the acpuclock controller

- reg-names: name of the bases for the above registers. "rcg_base", "pwr_base"

	     are expected.

- a5_cpu-supply: regulator to supply a5 cpu

- a5_mem-supply: regulator to supply a5 l2 cache



Example:

        qcom,acpuclk@f9010000 {

                compatible = "qcom,acpuclk-9625";

                reg = <0xf9010008 0x10>,

                      <0xf9008004 0x4>;

                reg-names = "rcg_base", "pwr_base";

                a5_cpu-supply = <&pm8019_l10_corner_ao>;

                a5_mem-supply = <&pm8019_l12_ao>;

        };

arch/arm/boot/dts/qti/Makefile

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@@ -28,13 +28,6 @@ dtb-$(CONFIG_ARCH_MSM8974) += msm8974-v1-cdp.dtb \ 
	msm8974pro-ac-pm8941-liquid.dtb \

	msm8974pro-ac-pm8941-mtp.dtb \

	msm8974pro-ac-pma8084-pm8941-mtp.dtb

dtb-$(CONFIG_ARCH_MSM9625) += msm9625-v1-cdp.dtb \

	msm9625-v1-mtp.dtb \

	msm9625-v1-rumi.dtb \

	msm9625-v2-cdp.dtb \

	msm9625-v2-mtp.dtb \

	msm9625-v2.1-mtp.dtb \

	msm9625-v2.1-cdp.dtb

dtb-$(CONFIG_ARCH_MSM8226) += msm8226-sim.dtb \

	msm8226-fluid.dtb \

	msm8226-v1-cdp.dtb \

arch/arm/boot/dts/qti/msm9625-cdp.dtsi

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/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#include "msm9625-display.dtsi"

#include "qpic-panel-ili-qvga.dtsi"



&soc {

	i2c@f9925000 {

		charger@57 {

			compatible = "summit,smb137c";

			reg = <0x57>;

			summit,chg-current-ma = <1500>;

			summit,term-current-ma = <50>;

			summit,pre-chg-current-ma = <100>;

			summit,float-voltage-mv = <4200>;

			summit,thresh-voltage-mv = <3000>;

			summit,recharge-thresh-mv = <75>;

			summit,system-voltage-mv = <4250>;

			summit,charging-timeout = <382>;

			summit,pre-charge-timeout = <48>;

			summit,therm-current-ua = <10>;

			summit,temperature-min = <4>; /*  0 C */

			summit,temperature-max = <3>; /* 45 C */

		};

	};



	wlan0: qca,wlan {

		cell-index = <0>;

		compatible = "qca,ar6004-hsic";

		qca,chip-pwd-l-gpios = <&msmgpio 62 0>;

		qca,pm-enable-gpios = <&pm8019_gpios 3 0x0>;

		qca,vdd-io-supply = <&pm8019_l11>;

	};



	qca,wlan_ar6003 {

		cell-index = <0>;

		compatible = "qca,ar6003-sdio";

		qca,chip-pwd-l-gpios = <&msmgpio 62 0>;

		qca,pm-enable-gpios = <&pm8019_gpios 3 0x0>;

		qca,vdd-io-supply = <&pm8019_l11>;

	};

};



/* PM8019 GPIO and MPP configuration */

&pm8019_gpios {

	gpio@c000 { /* GPIO 1 */

	};



	gpio@c100 { /* GPIO 2 */

	};



	gpio@c200 { /* GPIO 3 */

	};



	gpio@c300 { /* GPIO 4 */

		/* ext_2p95v regulator enable config */

		qcom,mode = <1>; /* Digital output */

		qcom,output-type = <0>; /* CMOS */

		qcom,invert = <0>; /* Output low */

		qcom,out-strength = <1>; /* Low */

		qcom,vin-sel = <2>; /* PM8019 L11 - 1.8V */

		qcom,src-sel = <0>; /* Constant */

		qcom,master-en = <1>; /* Enable GPIO */

	};



	gpio@c400 { /* GPIO 5 */

	};



	gpio@c500 { /* GPIO 6 */

	};

};



&pm8019_mpps {

	mpp@a000 { /* MPP 1 */

	};



	mpp@a100 { /* MPP 2 */

	};



	mpp@a200 { /* MPP 3 */

	};



	mpp@a300 { /* MPP 4 */

	};



	mpp@a400 { /* MPP 5 */

	};



	mpp@a500 { /* MPP 6 */

	};

};

arch/arm/boot/dts/qti/msm9625-coresight.dtsi

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/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



&soc {

	tmc_etr: tmc@fc322000 {

		compatible = "arm,coresight-tmc";

		reg = <0xfc322000 0x1000>,

		      <0xfc37c000 0x3000>;

		reg-names = "tmc-base", "bam-base";

		interrupts = <0 166 0>;

		interrupt-names = "byte-cntr-irq";



		qcom,memory-size = <0x20000>;



		coresight-id = <0>;

		coresight-name = "coresight-tmc-etr";

		coresight-nr-inports = <1>;

		coresight-ctis = <&cti0 &cti8>;

	};



	tpiu: tpiu@fc318000 {

		compatible = "arm,coresight-tpiu";

		reg = <0xfc318000 0x1000>;

		reg-names = "tpiu-base";



		coresight-id = <1>;

		coresight-name = "coresight-tpiu";

		coresight-nr-inports = <1>;



		vdd-supply = <&ext_2p95v>;

	};



	replicator: replicator@fc31c000 {

		compatible = "qcom,coresight-replicator";

		reg = <0xfc31c000 0x1000>;

		reg-names = "replicator-base";



		coresight-id = <2>;

		coresight-name = "coresight-replicator";

		coresight-nr-inports = <1>;

		coresight-outports = <0 1>;

		coresight-child-list = <&tmc_etr &tpiu>;

		coresight-child-ports = <0 0>;

	};



	tmc_etf: tmc@fc307000 {

		compatible = "arm,coresight-tmc";

		reg = <0xfc307000 0x1000>;

		reg-names = "tmc-base";



		coresight-id = <3>;

		coresight-name = "coresight-tmc-etf";

		coresight-nr-inports = <1>;

		coresight-outports = <0>;

		coresight-child-list = <&replicator>;

		coresight-child-ports = <0>;

		coresight-default-sink;

		coresight-ctis = <&cti0 &cti8>;

	};



	funnel_merg: funnel@fc31b000 {

		compatible = "arm,coresight-funnel";

		reg = <0xfc31b000 0x1000>;

		reg-names = "funnel-base";



		coresight-id = <4>;

		coresight-name = "coresight-funnel-merg";

		coresight-nr-inports = <2>;

		coresight-outports = <0>;

		coresight-child-list = <&tmc_etf>;

		coresight-child-ports = <0>;

	};



	funnel_in0: funnel@fc319000 {

		compatible = "arm,coresight-funnel";

		reg = <0xfc319000 0x1000>;

		reg-names = "funnel-base";



		coresight-id = <5>;

		coresight-name = "coresight-funnel-in0";

		coresight-nr-inports = <8>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_merg>;

		coresight-child-ports = <0>;

	};



	funnel_in1: funnel@fc31a000 {

		compatible = "arm,coresight-funnel";

		reg = <0xfc31a000 0x1000>;

		reg-names = "funnel-base";



		coresight-id = <6>;

		coresight-name = "coresight-funnel-in1";

		coresight-nr-inports = <8>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_merg>;

		coresight-child-ports = <1>;

	};



	stm: stm@fc321000 {

		compatible = "arm,coresight-stm";

		reg = <0xfc321000 0x1000>,

		      <0xfa280000 0x180000>;

		reg-names = "stm-base", "stm-data-base";



		coresight-id = <7>;

		coresight-name = "coresight-stm";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_in1>;

		coresight-child-ports = <7>;

	};



	etm0: etm@fc332000 {

		compatible = "arm,coresight-etm";

		reg = <0xfc332000 0x1000>;

		reg-names = "etm-base";



		coresight-id = <8>;

		coresight-name = "coresight-etm0";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_in0>;

		coresight-child-ports = <4>;



		qcom,round-robin;

	};



	audio_etm0 {

		compatible = "qcom,coresight-audio-etm";



		coresight-id = <9>;

		coresight-name = "coresight-audio-etm0";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_in0>;

		coresight-child-ports = <2>;

	};



	modem_etm0 {

		compatible = "qcom,coresight-modem-etm";



		coresight-id = <10>;

		coresight-name = "coresight-modem-etm0";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_in0>;

		coresight-child-ports = <1>;

	};



	rpm_etm0 {

		compatible = "qcom,coresight-rpm-etm";



		coresight-id = <11>;

		coresight-name = "coresight-rpm-etm0";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_in0>;

		coresight-child-ports = <0>;

	};



	csr: csr@fc302000 {

		compatible = "qcom,coresight-csr";

		reg = <0xfc302000 0x1000>;

		reg-names = "csr-base";



		coresight-id = <12>;

		coresight-name = "coresight-csr";

		coresight-nr-inports = <0>;



		qcom,blk-size = <1>;

	};



	cti0: cti@fc308000 {

		compatible = "arm,coresight-cti";

		reg = <0xfc308000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <13>;

		coresight-name = "coresight-cti0";

		coresight-nr-inports = <0>;

	};



	cti1: cti@fc309000 {

		compatible = "arm,coresight-cti";

		reg = <0xfc309000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <14>;

		coresight-name = "coresight-cti1";

		coresight-nr-inports = <0>;

	};



	cti2: cti@fc30a000 {

		compatible = "arm,coresight-cti";

		reg = <0xfc30a000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <15>;

		coresight-name = "coresight-cti2";

		coresight-nr-inports = <0>;

	};



	cti3: cti@fc30b000 {

		compatible = "arm,coresight-cti";

		reg = <0xfc30b000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <16>;

		coresight-name = "coresight-cti3";

		coresight-nr-inports = <0>;

	};



	cti4: cti@fc30c000 {

		compatible = "arm,coresight-cti";

		reg = <0xfc30c000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <17>;

		coresight-name = "coresight-cti4";

		coresight-nr-inports = <0>;

	};



	cti5: cti@fc30d000 {

		compatible = "arm,coresight-cti";

		reg = <0xfc30d000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <18>;

		coresight-name = "coresight-cti5";

		coresight-nr-inports = <0>;

	};



	cti6: cti@fc30e000 {

		compatible = "arm,coresight-cti";

		reg = <0xfc30e000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <19>;

		coresight-name = "coresight-cti6";

		coresight-nr-inports = <0>;

	};



	cti7: cti@fc30f000 {

		compatible = "arm,coresight-cti";

		reg = <0xfc30f000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <20>;

		coresight-name = "coresight-cti7";

		coresight-nr-inports = <0>;

	};



	cti8: cti@fc310000 {

		compatible = "arm,coresight-cti";

		reg = <0xfc310000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <21>;

		coresight-name = "coresight-cti8";

		coresight-nr-inports = <0>;

	};



	cti_cpu0: cti@fc333000 {

		compatible = "arm,coresight-cti";

		reg = <0xfc333000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <22>;

		coresight-name = "coresight-cti-cpu0";

		coresight-nr-inports = <0>;

	};



	cti_modem_cpu0: cti@fc350000 {

		compatible = "arm,coresight-cti";

		reg = <0xfc350000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <23>;

		coresight-name = "coresight-cti-modem-cpu0";

		coresight-nr-inports = <0>;

	};



	cti_audio_cpu0: cti@fc354000 {

		compatible = "arm,coresight-cti";

		reg = <0xfc354000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <24>;

		coresight-name = "coresight-cti-audio-cpu0";

		coresight-nr-inports = <0>;

	};



	cti_rpm_cpu0: cti@fc358000 {

		compatible = "arm,coresight-cti";

		reg = <0xfc358000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <25>;

		coresight-name = "coresight-cti-rpm-cpu0";

		coresight-nr-inports = <0>;

	};



	hwevent: hwevent@f9011038 {

		compatible = "qcom,coresight-hwevent";

		reg = <0xf9011038 0x8>,

		      <0xfd4ab160 0x80>,

		      <0xfc401600 0x80>;

		reg-names = "apcs-mux", "ppss-mux", "gcc-mux";



		coresight-id = <26>;

		coresight-name = "coresight-hwevent";

		coresight-nr-inports = <0>;

	};



	fuse: fuse@fc4be024 {

		compatible = "arm,coresight-fuse";

		reg = <0xfc4be024 0x8>;

		reg-names = "fuse-base";



		coresight-id = <27>;

		coresight-name = "coresight-fuse";

		coresight-nr-inports = <0>;

	};

};

arch/arm/boot/dts/qti/msm9625-display.dtsi

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/* Copyright (c) 2013, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



&soc {

	qcom,msm_qpic@f9ac0000 {

		compatible = "qcom,mdss_qpic";

		reg = <0xf9ac0000 0x24000>;

		reg-names = "qpic_base";

		interrupts = <0 251 0>;

	};

};