Merge "msm: mdss: Remove support for CSC_0 hardware" (34e0b666) · Commits · e / devices / android_kernel_sony_msm8994

drivers/video/msm/mdss/mdss_mdp.h

+2 −3

Original line number	Diff line number	Diff line
		@@ -805,9 +805,8 @@ int mdss_mdp_display_wait4pingpong(struct mdss_mdp_ctl *ctl);
		int mdss_mdp_display_wakeup_time(struct mdss_mdp_ctl *ctl,
		ktime_t *wakeup_time);

		int mdss_mdp_csc_setup(u32 block, u32 blk_idx, u32 tbl_idx, u32 csc_type);
		int mdss_mdp_csc_setup_data(u32 block, u32 blk_idx, u32 tbl_idx,
		struct mdp_csc_cfg *data);
		int mdss_mdp_csc_setup(u32 block, u32 blk_idx, u32 csc_type);
		int mdss_mdp_csc_setup_data(u32 block, u32 blk_idx, struct mdp_csc_cfg *data);

		int mdss_mdp_pp_init(struct device *dev);
		void mdss_mdp_pp_term(struct device *dev);

drivers/video/msm/mdss/mdss_mdp_hwio.h

+0 −1

Original line number	Diff line number	Diff line
		@@ -263,7 +263,6 @@ enum mdss_mdp_sspp_chroma_samp_type {
		#define MDSS_MDP_REG_SCALE_INIT_PHASE_X 0x220
		#define MDSS_MDP_REG_SCALE_INIT_PHASE_Y 0x224

		#define MDSS_MDP_REG_VIG_CSC_0_BASE 0x280
		#define MDSS_MDP_REG_VIG_CSC_1_BASE 0x320

		#define MDSS_MDP_REG_VIG_HIST_CTL_BASE 0x2C4

drivers/video/msm/mdss/mdss_mdp_intf_writeback.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -167,7 +167,7 @@ static int mdss_mdp_writeback_format_setup(struct mdss_mdp_writeback_ctx *ctx,
		chroma_samp = fmt->chroma_sample;

		if (ctx->type != MDSS_MDP_WRITEBACK_TYPE_ROTATOR && fmt->is_yuv) {
		mdss_mdp_csc_setup(MDSS_MDP_BLOCK_WB, ctx->wb_num, 0,
		mdss_mdp_csc_setup(MDSS_MDP_BLOCK_WB, ctx->wb_num,
		MDSS_MDP_CSC_RGB2YUV);
		opmode \|= (1 << 8) \| /* CSC_EN */
		(0 << 9) \| /* SRC_DATA=RGB */

drivers/video/msm/mdss/mdss_mdp_pp.c

+8 −13

Original line number	Diff line number	Diff line
		@@ -445,8 +445,7 @@ inline int linear_map(int in, int *out, int in_max, int out_max)

		}

		int mdss_mdp_csc_setup_data(u32 block, u32 blk_idx, u32 tbl_idx,
		struct mdp_csc_cfg *data)
		int mdss_mdp_csc_setup_data(u32 block, u32 blk_idx, struct mdp_csc_cfg *data)
		{
		int i, ret = 0;
		char __iomem base, addr;
		@@ -471,11 +470,7 @@ int mdss_mdp_csc_setup_data(u32 block, u32 blk_idx, u32 tbl_idx,
		break;
		}
		if (mdss_mdp_pipe_is_yuv(pipe)) {
		base = pipe->base;
		if (tbl_idx == 1)
		base += MDSS_MDP_REG_VIG_CSC_1_BASE;
		else
		base += MDSS_MDP_REG_VIG_CSC_0_BASE;
		base = pipe->base + MDSS_MDP_REG_VIG_CSC_1_BASE;
		} else {
		pr_err("non ViG pipe %d for CSC is not allowed\n",
		blk_idx);
		@@ -534,7 +529,7 @@ int mdss_mdp_csc_setup_data(u32 block, u32 blk_idx, u32 tbl_idx,
		return ret;
		}

		int mdss_mdp_csc_setup(u32 block, u32 blk_idx, u32 tbl_idx, u32 csc_type)
		int mdss_mdp_csc_setup(u32 block, u32 blk_idx, u32 csc_type)
		{
		struct mdp_csc_cfg *data;

		@@ -543,11 +538,11 @@ int mdss_mdp_csc_setup(u32 block, u32 blk_idx, u32 tbl_idx, u32 csc_type)
		return -ERANGE;
		}

		pr_debug("csc type=%d blk=%d idx=%d tbl=%d\n", csc_type,
		block, blk_idx, tbl_idx);
		pr_debug("csc type=%d blk=%d idx=%d\n", csc_type,
		block, blk_idx);

		data = &mdp_csc_convert[csc_type];
		return mdss_mdp_csc_setup_data(block, blk_idx, tbl_idx, data);
		return mdss_mdp_csc_setup_data(block, blk_idx, data);
		}

		static void pp_gamut_config(struct mdp_gamut_cfg_data *gamut_cfg,
		@@ -858,7 +853,7 @@ static int pp_vig_pipe_setup(struct mdss_mdp_pipe pipe, u32 op)
		* applied (i.e. dirty bit)
		*/
		mdss_mdp_csc_setup_data(MDSS_MDP_BLOCK_SSPP, pipe->num,
		1, &pipe->pp_cfg.csc_cfg);
		&pipe->pp_cfg.csc_cfg);
		} else {
		if (pipe->src_fmt->is_yuv) {
		opmode \|= (0 << 19) \| /* DST_DATA=RGB */
		@@ -869,7 +864,7 @@ static int pp_vig_pipe_setup(struct mdss_mdp_pipe pipe, u32 op)
		* is a previously configured pipe need to re-configure
		* CSC matrix
		*/
		mdss_mdp_csc_setup(MDSS_MDP_BLOCK_SSPP, pipe->num, 1,
		mdss_mdp_csc_setup(MDSS_MDP_BLOCK_SSPP, pipe->num,
		MDSS_MDP_CSC_YUV2RGB);
		}
		}