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Commit 33e913a6 authored by Taniya Das's avatar Taniya Das
Browse files

msm: clock-gcc: Add support for QOS ref clock 



This is a control register to generate the QOS signal from XO/4
clock. Add a gate clock to allow enable/disable of the clock.

Change-Id: Ifa63e235bc057bb1746b7cee3a92957631dbc859
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent aebe1f28

drivers/clk/qcom/clock-gcc-8909.c

+16 −0
Original line number Diff line number Diff line
@@ -64,6 +64,7 @@ static void __iomem *virt_bases[N_BASES]; 
#define GPLL2_USER_CTL					0x25010

#define GPLL2_CONFIG_CTL				0x25018

#define GPLL2_STATUS					0x25024

#define SNOC_QOSGEN					0x2601C

#define MSS_CFG_AHB_CBCR				0x49000

#define MSS_Q6_BIMC_AXI_CBCR				0x49004

#define QPIC_AHB_CBCR					0x3F01C
@@ -2127,6 +2128,18 @@ static struct branch_clk gcc_venus0_vcodec0_clk = { 
	},

};



static struct gate_clk gcc_snoc_qosgen_clk = {

	.en_mask = BIT(0),

	.en_reg = SNOC_QOSGEN,

	.base = &virt_bases[GCC_BASE],

	.c = {

		.dbg_name = "gcc_snoc_qosgen_clk",

		.ops = &clk_ops_gate,

		.flags = CLKFLAG_SKIP_HANDOFF,

		CLK_INIT(gcc_snoc_qosgen_clk.c),

	},

};



static struct mux_clk gcc_debug_mux;

static struct clk_ops clk_ops_debug_mux;
@@ -2493,6 +2506,9 @@ static struct clk_lookup msm_clocks_lookup[] = { 
	/* Reset clocks */

	CLK_LIST(gcc_usb2_hs_phy_only_clk),

	CLK_LIST(gcc_qusb2_phy_clk),



	/* QoS Reference clock */

	CLK_LIST(gcc_snoc_qosgen_clk),

};



static int add_dev_opp(struct clk *c, struct device *dev,

drivers/clk/qcom/clock-gcc-8916.c

+16 −0
Original line number Diff line number Diff line
@@ -56,6 +56,7 @@ static void __iomem *virt_bases[N_BASES]; 
#define GPLL1_USER_CTL					0x20010

#define GPLL1_CONFIG_CTL				0x20014

#define GPLL1_STATUS					0x2001C

#define SNOC_QOSGEN					0x2601C

#define GPLL2_MODE					0x4A000

#define GPLL2_L_VAL					0x4A004

#define GPLL2_M_VAL					0x4A008
@@ -2334,6 +2335,18 @@ static struct branch_clk gcc_venus0_vcodec0_clk = { 
	},

};



static struct gate_clk gcc_snoc_qosgen_clk = {

	.en_mask = BIT(0),

	.en_reg = SNOC_QOSGEN,

	.base = &virt_bases[GCC_BASE],

	.c = {

		.dbg_name = "gcc_snoc_qosgen_clk",

		.ops = &clk_ops_gate,

		.flags = CLKFLAG_SKIP_HANDOFF,

		CLK_INIT(gcc_snoc_qosgen_clk.c),

	},

};



static struct mux_clk gcc_debug_mux;

static struct clk_ops clk_ops_debug_mux;
@@ -2722,6 +2735,9 @@ static struct clk_lookup msm_clocks_lookup[] = { 
	CLK_LIST(gcc_crypto_ahb_clk),

	CLK_LIST(gcc_crypto_axi_clk),

	CLK_LIST(crypto_clk_src),



	/* QoS Reference clock */

	CLK_LIST(gcc_snoc_qosgen_clk),

};



static int msm_gcc_probe(struct platform_device *pdev)

include/dt-bindings/clock/msm-clocks-8909.h

+1 −0
Original line number Diff line number Diff line
@@ -163,6 +163,7 @@ 
#define clk_gcc_gtcu_ahb_bridge_clk		0x19d2c5fe

#define clk_gcc_bimc_gpu_clk			0x19922503

#define clk_gcc_bimc_gfx_clk			0x3edd69ad

#define clk_gcc_snoc_qosgen_clk			0x37d40ce2



#define clk_pixel_clk_src			0x8b6f83d8

#define clk_byte_clk_src			0x3a911c53

include/dt-bindings/clock/msm-clocks-8916.h

+1 −0
Original line number Diff line number Diff line
@@ -158,6 +158,7 @@ 
#define clk_gcc_gtcu_ahb_bridge_clk		0x19d2c5fe

#define clk_gcc_bimc_gpu_clk			0x19922503

#define clk_gcc_bimc_gfx_clk			0x3edd69ad

#define clk_gcc_snoc_qosgen_clk			0x37d40ce2



#define clk_pixel_clk_src			0x8b6f83d8

#define clk_byte_clk_src			0x3a911c53