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Commit 322aafa6 authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'x86-mrst-for-linus' of... 

Merge branch 'x86-mrst-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip

* 'x86-mrst-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (30 commits)
  x86, mrst: Fix whitespace breakage in apb_timer.c
  x86, mrst: Fix APB timer per cpu clockevent
  x86, mrst: Remove X86_MRST dependency on PCI_IOAPIC
  x86, olpc: Use pci subarch init for OLPC
  x86, pci: Add arch_init to x86_init abstraction
  x86, mrst: Add Kconfig dependencies for Moorestown
  x86, pci: Exclude Moorestown PCI code if CONFIG_X86_MRST=n
  x86, numaq: Make CONFIG_X86_NUMAQ depend on CONFIG_PCI
  x86, pci: Add sanity check for PCI fixed bar probing
  x86, legacy_irq: Remove duplicate vector assigment
  x86, legacy_irq: Remove left over nr_legacy_irqs
  x86, mrst: Platform clock setup code
  x86, apbt: Moorestown APB system timer driver
  x86, mrst: Add vrtc platform data setup code
  x86, mrst: Add platform timer info parsing code
  x86, mrst: Fill in PCI functions in x86_init layer
  x86, mrst: Add dummy legacy pic to platform setup
  x86/PCI: Moorestown PCI support
  x86, ioapic: Add dummy ioapic functions
  x86, ioapic: Early enable ioapic for timer irq
  ...

Fixed up semantic conflict of new clocksources due to commit
17622339 ("clocksource: add argument to resume callback").
parents dd04265b c7bbf52a

Documentation/kernel-parameters.txt

+6 −0
Original line number Diff line number Diff line
@@ -2834,6 +2834,12 @@ and is between 256 and 4096 characters. It is defined in the file 
			default x2apic cluster mode on platforms

			supporting x2apic.



	x86_mrst_timer= [X86-32,APBT]

			Choose timer option for x86 Moorestown MID platform.

			Two valid options are apbt timer only and lapic timer

			plus one apbt timer for broadcast timer.

			x86_mrst_timer=apbt_only | lapic_and_apbt



	xd=		[HW,XT] Original XT pre-IDE (RLL encoded) disks.

	xd_geo=		See header of drivers/block/xd.c.

arch/x86/Kconfig

+15 −0
Original line number Diff line number Diff line
@@ -393,8 +393,12 @@ config X86_ELAN 


config X86_MRST

       bool "Moorestown MID platform"

	depends on PCI

	depends on PCI_GOANY

	depends on X86_32

	depends on X86_EXTENDED_PLATFORM

	depends on X86_IO_APIC

	select APB_TIMER

	---help---

	  Moorestown is Intel's Low Power Intel Architecture (LPIA) based Moblin

	  Internet Device(MID) platform. Moorestown consists of two chips:
@@ -429,6 +433,7 @@ config X86_32_NON_STANDARD 
config X86_NUMAQ

	bool "NUMAQ (IBM/Sequent)"

	depends on X86_32_NON_STANDARD

	depends on PCI

	select NUMA

	select X86_MPPARSE

	---help---
@@ -629,6 +634,16 @@ config HPET_EMULATE_RTC 
	def_bool y

	depends on HPET_TIMER && (RTC=y || RTC=m || RTC_DRV_CMOS=m || RTC_DRV_CMOS=y)



config APB_TIMER

       def_bool y if MRST

       prompt "Langwell APB Timer Support" if X86_MRST

       help

         APB timer is the replacement for 8254, HPET on X86 MID platforms.

         The APBT provides a stable time base on SMP

         systems, unlike the TSC, but it is more expensive to access,

         as it is off-chip. APB timers are always running regardless of CPU

         C states, they are used as per CPU clockevent device when possible.



# Mark as embedded because too many people got it wrong.

# The code disables itself when not needed.

config DMI

arch/x86/include/asm/apb_timer.h

0 → 100644
+70 −0
Original line number Diff line number Diff line 
/*

 * apb_timer.h: Driver for Langwell APB timer based on Synopsis DesignWare

 *

 * (C) Copyright 2009 Intel Corporation

 * Author: Jacob Pan (jacob.jun.pan@intel.com)

 *

 * This program is free software; you can redistribute it and/or

 * modify it under the terms of the GNU General Public License

 * as published by the Free Software Foundation; version 2

 * of the License.

 *

 * Note:

 */



#ifndef ASM_X86_APBT_H

#define ASM_X86_APBT_H

#include <linux/sfi.h>



#ifdef CONFIG_APB_TIMER



/* Langwell DW APB timer registers */

#define APBTMR_N_LOAD_COUNT    0x00

#define APBTMR_N_CURRENT_VALUE 0x04

#define APBTMR_N_CONTROL       0x08

#define APBTMR_N_EOI           0x0c

#define APBTMR_N_INT_STATUS    0x10



#define APBTMRS_INT_STATUS     0xa0

#define APBTMRS_EOI            0xa4

#define APBTMRS_RAW_INT_STATUS 0xa8

#define APBTMRS_COMP_VERSION   0xac

#define APBTMRS_REG_SIZE       0x14



/* register bits */

#define APBTMR_CONTROL_ENABLE  (1<<0)

#define APBTMR_CONTROL_MODE_PERIODIC   (1<<1) /*1: periodic 0:free running */

#define APBTMR_CONTROL_INT     (1<<2)



/* default memory mapped register base */

#define LNW_SCU_ADDR           0xFF100000

#define LNW_EXT_TIMER_OFFSET   0x1B800

#define APBT_DEFAULT_BASE      (LNW_SCU_ADDR+LNW_EXT_TIMER_OFFSET)

#define LNW_EXT_TIMER_PGOFFSET         0x800



/* APBT clock speed range from PCLK to fabric base, 25-100MHz */

#define APBT_MAX_FREQ          50

#define APBT_MIN_FREQ          1

#define APBT_MMAP_SIZE         1024



#define APBT_DEV_USED  1



extern void apbt_time_init(void);

extern struct clock_event_device *global_clock_event;

extern unsigned long apbt_quick_calibrate(void);

extern int arch_setup_apbt_irqs(int irq, int trigger, int mask, int cpu);

extern void apbt_setup_secondary_clock(void);

extern unsigned int boot_cpu_id;

extern int disable_apbt_percpu;



extern struct sfi_timer_table_entry *sfi_get_mtmr(int hint);

extern void sfi_free_mtmr(struct sfi_timer_table_entry *mtmr);

extern int sfi_mtimer_num;



#else /* CONFIG_APB_TIMER */



static inline unsigned long apbt_quick_calibrate(void) {return 0; }

static inline void apbt_time_init(void) {return 0; }



#endif

#endif /* ASM_X86_APBT_H */

arch/x86/include/asm/hw_irq.h

+0 −7
Original line number Diff line number Diff line
@@ -53,13 +53,6 @@ extern void threshold_interrupt(void); 
extern void call_function_interrupt(void);

extern void call_function_single_interrupt(void);



/* PIC specific functions */

extern void disable_8259A_irq(unsigned int irq);

extern void enable_8259A_irq(unsigned int irq);

extern int i8259A_irq_pending(unsigned int irq);

extern void make_8259A_irq(unsigned int irq);

extern void init_8259A(int aeoi);



/* IOAPIC */

#define IO_APIC_IRQ(x) (((x) >= NR_IRQS_LEGACY) || ((1<<(x)) & io_apic_irqs))

extern unsigned long io_apic_irqs;

arch/x86/include/asm/i8259.h

+12 −7
Original line number Diff line number Diff line
@@ -26,11 +26,6 @@ extern unsigned int cached_irq_mask; 


extern raw_spinlock_t i8259A_lock;



extern void init_8259A(int auto_eoi);

extern void enable_8259A_irq(unsigned int irq);

extern void disable_8259A_irq(unsigned int irq);

extern unsigned int startup_8259A_irq(unsigned int irq);



/* the PIC may need a careful delay on some platforms, hence specific calls */

static inline unsigned char inb_pic(unsigned int port)

{
@@ -57,7 +52,17 @@ static inline void outb_pic(unsigned char value, unsigned int port) 


extern struct irq_chip i8259A_chip;



extern void mask_8259A(void);

extern void unmask_8259A(void);

struct legacy_pic {

	int nr_legacy_irqs;

	struct irq_chip *chip;

	void (*mask_all)(void);

	void (*restore_mask)(void);

	void (*init)(int auto_eoi);

	int (*irq_pending)(unsigned int irq);

	void (*make_irq)(unsigned int irq);

};



extern struct legacy_pic *legacy_pic;

extern struct legacy_pic null_legacy_pic;



#endif /* _ASM_X86_I8259_H */