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Commit 31190d62 authored by Catalin Marinas's avatar Catalin Marinas Committed by Laura Abbott
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arm64: Fix DMA range invalidation for cache line unaligned buffers 



If the buffer needing cache invalidation for inbound DMA does start or
end on a cache line aligned address, we need to use the non-destructive
clean&invalidate operation. This issue was introduced by commit
7363590d2c46 (arm64: Implement coherent DMA API based on swiotlb).

Change-Id: Ic7f3fbb10f1dc944a6fda9c7b399b1d25cb26ee8
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Reported-by: default avatarJon Medhurst (Tixy) <tixy@linaro.org>
Git-commit: ebf81a938dade3b450eb11c57fa744cfac4b523f
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git


Signed-off-by: default avatarLaura Abbott <lauraa@codeaurora.org>
parent 0a0b25b6

arch/arm64/mm/cache.S

+11 −4
Original line number Diff line number Diff line
@@ -210,12 +210,19 @@ ENDPROC(__flush_dcache_area) 
ENTRY(__dma_inv_range)

	dcache_line_size x2, x3

	sub	x3, x2, #1

	bic	x0, x0, x3

	tst	x1, x3				// end cache line aligned?

	bic	x1, x1, x3

1:	dc	ivac, x0			// invalidate D / U line

	add	x0, x0, x2

	b.eq	1f

	dc	civac, x1			// clean & invalidate D / U line

1:	tst	x0, x3				// start cache line aligned?

	bic	x0, x0, x3

	b.eq	2f

	dc	civac, x0			// clean & invalidate D / U line

	b	3f

2:	dc	ivac, x0			// invalidate D / U line

3:	add	x0, x0, x2

	cmp	x0, x1

	b.lo	1b

	b.lo	2b

	dsb	sy

	ret

ENDPROC(__dma_inv_range)