Loading arch/arm/mach-msm/acpuclock-8226.c +19 −2 Original line number Diff line number Diff line Loading @@ -106,7 +106,23 @@ static struct clkctl_acpu_speed acpu_freq_tbl_8226_1p5[] = { { 1, 1305600, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 1, 1344000, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 1, 1401600, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, /* No support for 1p5 GHz yet */ { 1, 1497600, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 0 } }; static struct clkctl_acpu_speed acpu_freq_tbl_8226_1p6[] = { { 1, 300000, PLL0, 4, 2, CPR_CORNER_SVS, 0, 4 }, { 1, 384000, ACPUPLL, 5, 2, CPR_CORNER_SVS, 0, 4 }, { 1, 600000, PLL0, 4, 0, CPR_CORNER_NORMAL, 0, 6 }, { 1, 787200, ACPUPLL, 5, 0, CPR_CORNER_NORMAL, 0, 7 }, { 1, 998400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 1, 1094400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 1, 1190400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 1, 1305600, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 1, 1344000, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 1, 1401600, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 1, 1497600, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 1, 1593600, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 0 } }; Loading @@ -125,8 +141,9 @@ static struct clkctl_acpu_speed *pvs_tables_8226[NUM_SPEED_BIN] = { [6] = acpu_freq_tbl_8226_1p2, [2] = acpu_freq_tbl_8226_1p4, [5] = acpu_freq_tbl_8226_1p4, [3] = acpu_freq_tbl_8226_1p5, [4] = acpu_freq_tbl_8226_1p5, [7] = acpu_freq_tbl_8226_1p5, [1] = acpu_freq_tbl_8226_1p6, }; static struct acpuclk_drv_data drv_data = { Loading arch/arm/mach-msm/clock-8226.c +2 −0 Original line number Diff line number Diff line Loading @@ -2767,6 +2767,8 @@ static struct pll_freq_tbl apcs_pll_freq[] = { F_APCS_PLL(1305600000, 68, 0x0, 0x1, 0x0, 0x0, 0x0), F_APCS_PLL(1344000000, 70, 0x0, 0x1, 0x0, 0x0, 0x0), F_APCS_PLL(1401600000, 73, 0x0, 0x1, 0x0, 0x0, 0x0), F_APCS_PLL(1497600000, 78, 0x0, 0x1, 0x0, 0x0, 0x0), F_APCS_PLL(1593600000, 83, 0x0, 0x1, 0x0, 0x0, 0x0), PLL_F_END }; Loading Loading
arch/arm/mach-msm/acpuclock-8226.c +19 −2 Original line number Diff line number Diff line Loading @@ -106,7 +106,23 @@ static struct clkctl_acpu_speed acpu_freq_tbl_8226_1p5[] = { { 1, 1305600, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 1, 1344000, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 1, 1401600, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, /* No support for 1p5 GHz yet */ { 1, 1497600, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 0 } }; static struct clkctl_acpu_speed acpu_freq_tbl_8226_1p6[] = { { 1, 300000, PLL0, 4, 2, CPR_CORNER_SVS, 0, 4 }, { 1, 384000, ACPUPLL, 5, 2, CPR_CORNER_SVS, 0, 4 }, { 1, 600000, PLL0, 4, 0, CPR_CORNER_NORMAL, 0, 6 }, { 1, 787200, ACPUPLL, 5, 0, CPR_CORNER_NORMAL, 0, 7 }, { 1, 998400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 1, 1094400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 1, 1190400, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 1, 1305600, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 1, 1344000, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 1, 1401600, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 1, 1497600, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 1, 1593600, ACPUPLL, 5, 0, CPR_CORNER_TURBO, 0, 7 }, { 0 } }; Loading @@ -125,8 +141,9 @@ static struct clkctl_acpu_speed *pvs_tables_8226[NUM_SPEED_BIN] = { [6] = acpu_freq_tbl_8226_1p2, [2] = acpu_freq_tbl_8226_1p4, [5] = acpu_freq_tbl_8226_1p4, [3] = acpu_freq_tbl_8226_1p5, [4] = acpu_freq_tbl_8226_1p5, [7] = acpu_freq_tbl_8226_1p5, [1] = acpu_freq_tbl_8226_1p6, }; static struct acpuclk_drv_data drv_data = { Loading
arch/arm/mach-msm/clock-8226.c +2 −0 Original line number Diff line number Diff line Loading @@ -2767,6 +2767,8 @@ static struct pll_freq_tbl apcs_pll_freq[] = { F_APCS_PLL(1305600000, 68, 0x0, 0x1, 0x0, 0x0, 0x0), F_APCS_PLL(1344000000, 70, 0x0, 0x1, 0x0, 0x0, 0x0), F_APCS_PLL(1401600000, 73, 0x0, 0x1, 0x0, 0x0, 0x0), F_APCS_PLL(1497600000, 78, 0x0, 0x1, 0x0, 0x0, 0x0), F_APCS_PLL(1593600000, 83, 0x0, 0x1, 0x0, 0x0, 0x0), PLL_F_END }; Loading