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Commit 2fd665de authored by Ke Liu's avatar Ke Liu
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ARM: dts: msm: configure MEM ACC type registers for mem_acc0 for msm8994 



MEM ACC type registers for mem_acc0 regulator needs to be configured
during APC mode switch and acc-l1 selector register configuration is not
required to be configured for msm8994. Hence update the configuration for
mem_acc0 regulator.

CRs-Fixed: 780594
CRs-Fixed: 780605
Change-Id: I848bbf7ae0792b43fbb62b4a7b47be77d318d230
Signed-off-by: default avatarKe Liu <keliu@codeaurora.org>
parent d59167ed

arch/arm/boot/dts/qcom/msm8994-regulator.dtsi

+9 −5
Original line number Diff line number Diff line 
/* Copyright (c) 2014, The Linux Foundation. All rights reserved.

/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -564,14 +564,18 @@ 
&soc {

	mem_acc0_vreg_corner: mem-acc0-regulator {

		compatible = "qcom,mem-acc-regulator";

		reg = <0xf9112144 0x4>;

		reg-names = "acc-sel-l1";

		reg = <0xf900d084 1>, <0xf900d088 1>,

			<0xf900d08c 1>, <0xf900d090 1>;

		reg-names = "mem-acc-type1", "mem-acc-type2",

			"mem-acc-type3", "mem-acc-type4";

		regulator-name = "mem_acc0_corner";

		regulator-min-microvolt = <1>;

		regulator-max-microvolt = <4>;

		qcom,corner-acc-map = <1 1 0 0>;

		qcom,acc-sel-l1-bit-pos = <0>;

		qcom,acc-sel-l1-bit-size = <1>;

		qcom,mem-acc-type1 = <0x02 0x02 0x00 0x00>;

		qcom,mem-acc-type2 = <0x02 0x02 0x00 0x00>;

		qcom,mem-acc-type3 = <0x02 0x02 0x00 0x00>;

		qcom,mem-acc-type4 = <0x02 0x02 0x00 0x00>;

	};



	mem_acc1_vreg_corner: mem-acc1-regulator {