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Commit 2e72dfc5 authored by Yaniv Gardi's avatar Yaniv Gardi
Browse files

scsi: ufs-msm: phy configuration to support rate B 



This change adds phy configuration to support working in rate B
in case vendor power-mode preferences are pre-defined to work in
rate B.
Note: This change doesn't configure the default working rate
to be rate B, but only adds the support to do so.

Change-Id: Iec896917f9c76dcc3b5383c211871c7edf215b44
Signed-off-by: default avatarYaniv Gardi <ygardi@codeaurora.org>
parent 614d6d7e

drivers/scsi/ufs/ufs-msm.c

+71 −20
Original line number Original line Diff line number Diff line
@@ -27,8 +27,24 @@ 
#include "unipro.h"

#include "unipro.h"

#include "ufs-msm.h"

#include "ufs-msm.h"





/* vendor specific pre-defined parameters */

#define SLOW 1

#define FAST 2





static struct msm_ufs_phy_calibration phy_cal_table[] = {

#define UFS_MSM_LIMIT_NUM_LANES_RX	2

#define UFS_MSM_LIMIT_NUM_LANES_TX	1

#define UFS_MSM_LIMIT_HSGEAR_RX	UFS_HS_G2

#define UFS_MSM_LIMIT_HSGEAR_TX	UFS_HS_G2

#define UFS_MSM_LIMIT_PWMGEAR_RX	UFS_PWM_G4

#define UFS_MSM_LIMIT_PWMGEAR_TX	UFS_PWM_G4

#define UFS_MSM_LIMIT_RX_PWR_PWM	SLOW_MODE

#define UFS_MSM_LIMIT_TX_PWR_PWM	SLOW_MODE

#define UFS_MSM_LIMIT_RX_PWR_HS	FAST_MODE

#define UFS_MSM_LIMIT_TX_PWR_HS	FAST_MODE

#define UFS_MSM_LIMIT_HS_RATE		PA_HS_MODE_A

#define UFS_MSM_LIMIT_DESIRED_MODE	FAST



static struct msm_ufs_phy_calibration phy_cal_table_rate_A[] = {

	{

	{

		.cfg_value = 0x01,

		.cfg_value = 0x01,

		.reg_offset = UFS_PHY_POWER_DOWN_CONTROL,

		.reg_offset = UFS_PHY_POWER_DOWN_CONTROL,
@@ -635,6 +651,49 @@ static struct msm_ufs_phy_calibration phy_cal_table[] = { 
	},

	},

};

};





static struct msm_ufs_phy_calibration phy_cal_table_rate_B[] = {

	{

		.cfg_value = 0x03,

		.reg_offset = QSERDES_COM_PLL_CLKEPDIV,

	},

	{

		.cfg_value = 0x98,

		.reg_offset = QSERDES_COM_DEC_START1,

	},

	{

		.cfg_value = 0x03,

		.reg_offset = QSERDES_COM_DEC_START2,

	},

	{

		.cfg_value = 0x80,

		.reg_offset = QSERDES_COM_DIV_FRAC_START1,

	},

	{

		.cfg_value = 0x80,

		.reg_offset = QSERDES_COM_DIV_FRAC_START2,

	},

	{

		.cfg_value = 0x10,

		.reg_offset = QSERDES_COM_DIV_FRAC_START3,

	},

	{

		.cfg_value = 0x65,

		.reg_offset = QSERDES_COM_PLLLOCK_CMP1,

	},

	{

		.cfg_value = 0x1E,

		.reg_offset = QSERDES_COM_PLLLOCK_CMP2,

	},

	{

		.cfg_value = 0x00,

		.reg_offset = QSERDES_COM_PLLLOCK_CMP3,

	},

	{

		.cfg_value = 0x03,

		.reg_offset = QSERDES_COM_PLLLOCK_CMP_EN,

	},

};



static struct msm_ufs_phy *msm_get_ufs_phy(struct device *dev)

static struct msm_ufs_phy *msm_get_ufs_phy(struct device *dev)

{

{

	int err  = -EPROBE_DEFER;

	int err  = -EPROBE_DEFER;
@@ -840,13 +899,22 @@ out: 




static void msm_ufs_phy_calibrate(struct msm_ufs_phy *phy)

static void msm_ufs_phy_calibrate(struct msm_ufs_phy *phy)

{

{

	struct msm_ufs_phy_calibration *tbl = phy_cal_table;

	struct msm_ufs_phy_calibration *tbl = phy_cal_table_rate_A;

	int tbl_size = ARRAY_SIZE(phy_cal_table);

	int tbl_size = ARRAY_SIZE(phy_cal_table_rate_A);

	int i;

	int i;





	for (i = 0; i < tbl_size; i++)

	for (i = 0; i < tbl_size; i++)

		writel_relaxed(tbl[i].cfg_value, phy->mmio + tbl[i].reg_offset);

		writel_relaxed(tbl[i].cfg_value, phy->mmio + tbl[i].reg_offset);





	if (UFS_MSM_LIMIT_HS_RATE == PA_HS_MODE_B) {

		tbl = phy_cal_table_rate_B;

		tbl_size = ARRAY_SIZE(phy_cal_table_rate_B);



		for (i = 0; i < tbl_size; i++)

			writel_relaxed(tbl[i].cfg_value,

					phy->mmio + tbl[i].reg_offset);

	}



	/* flush buffered writes */

	/* flush buffered writes */

	mb();

	mb();

}

}
@@ -1218,23 +1286,6 @@ static int msm_ufs_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) 
	return msm_ufs_phy_power_on(phy);

	return msm_ufs_phy_power_on(phy);

}

}





/* vendor specific pre-defined parameters */

#define SLOW 1

#define FAST 2



#define UFS_MSM_LIMIT_NUM_LANES_RX	2

#define UFS_MSM_LIMIT_NUM_LANES_TX	1

#define UFS_MSM_LIMIT_HSGEAR_RX	UFS_HS_G2

#define UFS_MSM_LIMIT_HSGEAR_TX	UFS_HS_G2

#define UFS_MSM_LIMIT_PWMGEAR_RX	UFS_PWM_G4

#define UFS_MSM_LIMIT_PWMGEAR_TX	UFS_PWM_G4

#define UFS_MSM_LIMIT_RX_PWR_PWM	SLOW_MODE

#define UFS_MSM_LIMIT_TX_PWR_PWM	SLOW_MODE

#define UFS_MSM_LIMIT_RX_PWR_HS	FAST_MODE

#define UFS_MSM_LIMIT_TX_PWR_HS	FAST_MODE

#define UFS_MSM_LIMIT_HS_RATE		PA_HS_MODE_A

#define UFS_MSM_LIMIT_DESIRED_MODE	FAST



struct ufs_msm_dev_params {

struct ufs_msm_dev_params {

	u32 pwm_rx_gear;	/* pwm rx gear to work in */

	u32 pwm_rx_gear;	/* pwm rx gear to work in */

	u32 pwm_tx_gear;	/* pwm tx gear to work in */

	u32 pwm_tx_gear;	/* pwm tx gear to work in */