Loading arch/arm/boot/dts/qcom/msm8939-common.dtsi +22 −2 Original line number Diff line number Diff line Loading @@ -1541,24 +1541,44 @@ }; &gdsc_venus { clock-names = "bus_clk", "core_clk", "core0_clk", "core1_clk"; clocks = <&clock_gcc clk_gcc_venus0_axi_clk>, <&clock_gcc clk_gcc_venus0_vcodec0_clk>, <&clock_gcc clk_gcc_venus0_core0_vcodec0_clk>, <&clock_gcc clk_gcc_venus0_core1_vcodec0_clk>; status = "okay"; }; &gdsc_mdss { clock-names = "core_clk", "bus_clk"; clocks = <&clock_gcc clk_gcc_mdss_mdp_clk>, <&clock_gcc clk_gcc_mdss_axi_clk>; status = "okay"; }; &gdsc_jpeg { clock-names = "core_clk", "bus_clk"; clocks = <&clock_gcc clk_gcc_camss_jpeg0_clk>, <&clock_gcc clk_gcc_camss_jpeg_axi_clk>; status = "okay"; }; &gdsc_vfe { clock-names = "core_clk", "bus_clk", "micro_clk", "cpp_clk", "csi_clk"; clocks = <&clock_gcc clk_gcc_camss_vfe0_clk>, <&clock_gcc clk_gcc_camss_vfe_axi_clk>, <&clock_gcc clk_gcc_camss_micro_ahb_clk>, <&clock_gcc clk_gcc_camss_cpp_clk>, <&clock_gcc clk_gcc_camss_csi_vfe0_clk>; status = "okay"; }; &gdsc_oxili_gx { clock-names = "core_clk"; clocks = <&clock_gcc clk_gfx3d_clk_src>; clock-names = "core_clk", "gmem_clk"; clocks = <&clock_gcc clk_gfx3d_clk_src>, <&clock_gcc clk_gcc_oxili_gmem_clk>; qcom,enable-root-clk; status = "okay"; }; Loading Loading
arch/arm/boot/dts/qcom/msm8939-common.dtsi +22 −2 Original line number Diff line number Diff line Loading @@ -1541,24 +1541,44 @@ }; &gdsc_venus { clock-names = "bus_clk", "core_clk", "core0_clk", "core1_clk"; clocks = <&clock_gcc clk_gcc_venus0_axi_clk>, <&clock_gcc clk_gcc_venus0_vcodec0_clk>, <&clock_gcc clk_gcc_venus0_core0_vcodec0_clk>, <&clock_gcc clk_gcc_venus0_core1_vcodec0_clk>; status = "okay"; }; &gdsc_mdss { clock-names = "core_clk", "bus_clk"; clocks = <&clock_gcc clk_gcc_mdss_mdp_clk>, <&clock_gcc clk_gcc_mdss_axi_clk>; status = "okay"; }; &gdsc_jpeg { clock-names = "core_clk", "bus_clk"; clocks = <&clock_gcc clk_gcc_camss_jpeg0_clk>, <&clock_gcc clk_gcc_camss_jpeg_axi_clk>; status = "okay"; }; &gdsc_vfe { clock-names = "core_clk", "bus_clk", "micro_clk", "cpp_clk", "csi_clk"; clocks = <&clock_gcc clk_gcc_camss_vfe0_clk>, <&clock_gcc clk_gcc_camss_vfe_axi_clk>, <&clock_gcc clk_gcc_camss_micro_ahb_clk>, <&clock_gcc clk_gcc_camss_cpp_clk>, <&clock_gcc clk_gcc_camss_csi_vfe0_clk>; status = "okay"; }; &gdsc_oxili_gx { clock-names = "core_clk"; clocks = <&clock_gcc clk_gfx3d_clk_src>; clock-names = "core_clk", "gmem_clk"; clocks = <&clock_gcc clk_gfx3d_clk_src>, <&clock_gcc clk_gcc_oxili_gmem_clk>; qcom,enable-root-clk; status = "okay"; }; Loading