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Commit 2dad0372 authored by Subbaraman Narayanamurthy's avatar Subbaraman Narayanamurthy
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ARM: dts: msm: configure MEM ACC type registers for mem_acc1 for msm8994 



MEM ACC type registers for mem_acc1 regulator needs to be configured
during APC1 mode switch and acc-l1-selector register configuration
is not required for msm8994. Hence update the configuration for
mem_acc1 regulator.

CRs-Fixed: 780594
CRs-Fixed: 780605
Change-Id: I2d0a9911cda3e8e086aee3188fc39cda7580037a
Signed-off-by: default avatarSubbaraman Narayanamurthy <subbaram@codeaurora.org>
parent c84f1f0f

arch/arm/boot/dts/qcom/msm8994-regulator.dtsi

+8 −4
Original line number Diff line number Diff line
@@ -580,14 +580,18 @@ 


	mem_acc1_vreg_corner: mem-acc1-regulator {

		compatible = "qcom,mem-acc-regulator";

		reg = <0xf9112144 0x4>;

		reg-names = "acc-sel-l1";

		reg = <0xf900f084 1>, <0xf900f088 1>,

			<0xf900f08c 1>, <0xf900f090 1>;

		reg-names = "mem-acc-type1", "mem-acc-type2",

			"mem-acc-type3", "mem-acc-type4";

		regulator-name = "mem_acc1_corner";

		regulator-min-microvolt = <1>;

		regulator-max-microvolt = <4>;

		qcom,corner-acc-map = <1 1 0 0>;

		qcom,acc-sel-l1-bit-pos = <1>;

		qcom,acc-sel-l1-bit-size = <1>;

		qcom,mem-acc-type1 = <0x02 0x02 0x06 0x06>;

		qcom,mem-acc-type2 = <0x02 0x02 0x06 0x06>;

		qcom,mem-acc-type3 = <0x02 0x02 0x06 0x06>;

		qcom,mem-acc-type4 = <0x0b 0x0b 0x0b 0x0b>;

	};



	apc0_vreg_corner: regulator@f9019000 {