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Commit 2d7d9603 authored by Stepan Moskovchenko's avatar Stepan Moskovchenko
Browse files

ARM: dts: msm: Add CPU / L2 clock control nodes for 8992 



Add the CPU ACC and L2 clock control nodes to the 8992
device tree, and configure the CPU nodes to refer to their
corresponding ACC / L2 nodes to allow booting the secondary
CPUs using the full boot chain.

Change-Id: I24a469614d8e1ac9f0909abe271fc162face7192
Signed-off-by: default avatarStepan Moskovchenko <stepanm@codeaurora.org>
parent 2d5e05d2

arch/arm/boot/dts/qcom/msm8992.dtsi

+68 −12
Original line number Diff line number Diff line
@@ -67,12 +67,13 @@ 
			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x06000000>;

			enable-method = "qcom,8994-arm-cortex-acc";

			qcom,acc = <&acc0>;

			next-level-cache = <&L2_0>;

			L2_0: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-level = <2>;

			      power-domain = <&l2ccc_0>;

			};

		};
@@ -80,8 +81,8 @@ 
			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x1>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x06000000>;

			enable-method = "qcom,8994-arm-cortex-acc";

			qcom,acc = <&acc1>;

			next-level-cache = <&L2_0>;

		};
@@ -89,8 +90,8 @@ 
			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x2>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x06000000>;

			enable-method = "qcom,8994-arm-cortex-acc";

			qcom,acc = <&acc2>;

			next-level-cache = <&L2_0>;

		};
@@ -98,8 +99,8 @@ 
			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x3>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x06000000>;

			enable-method = "qcom,8994-arm-cortex-acc";

			qcom,acc = <&acc3>;

			next-level-cache = <&L2_0>;

		};
@@ -107,12 +108,13 @@ 
			device_type = "cpu";

			compatible = "arm,cortex-a57";

			reg = <0x100>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x06000000>;

			enable-method = "qcom,8994-arm-cortex-acc";

			qcom,acc = <&acc4>;

			next-level-cache = <&L2_1>;

			L2_1: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-level = <2>;

			      power-domain = <&l2ccc_1>;

			};

		};
@@ -120,8 +122,8 @@ 
			device_type = "cpu";

			compatible = "arm,cortex-a57";

			reg = <0x101>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x06000000>;

			enable-method = "qcom,8994-arm-cortex-acc";

			qcom,acc = <&acc5>;

			next-level-cache = <&L2_1>;

		};

	};
@@ -243,6 +245,60 @@ 
		};

	};



	acc0:clock-controller@f9070000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0xf9070000 0x1000>,

		      <0xf908b000 0x1000>,

		      <0xf900b000 0x1000>;

	};



	acc1:clock-controller@f9071000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0xf9071000 0x1000>,

		      <0xf909b000 0x1000>,

		      <0xf900b000 0x1000>;

	};



	acc2:clock-controller@f9072000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0xf9072000 0x1000>,

		      <0xf90ab000 0x1000>,

		      <0xf900b000 0x1000>;

	};



	acc3:clock-controller@f9073000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0xf9073000 0x1000>,

		      <0xf90bb000 0x1000>,

		      <0xf900b000 0x1000>;

	};



	acc4:clock-controller@f9074000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0xf9074000 0x1000>,

		      <0xf90cb000 0x1000>,

		      <0xf900b000 0x1000>;

	};



	acc5:clock-controller@f9075000 {

		compatible = "qcom,arm-cortex-acc";

		reg = <0xf9075000 0x1000>,

		      <0xf90db000 0x1000>,

		      <0xf900b000 0x1000>;

	};



	l2ccc_0: clock-controller@f900d000 {

		compatible = "qcom,8994-l2ccc";

		reg = <0xf900d000 0x1000>,

		      <0xf911210c 0x4>;

	};



	l2ccc_1: clock-controller@f900f000 {

		compatible = "qcom,8994-l2ccc";

		reg = <0xf900f000 0x1000>,

		      <0xf911210c 0x4>;

	};



	arm64-cpu-erp@f9100000 {

		compatible = "arm,arm64-cpu-erp";

		reg = <0xf9100000 0x1000>;