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Commit 2bc49410 authored by Joonwoo Park's avatar Joonwoo Park Committed by Bhalchandra Gajare
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ASoC: wcd9320: Configure codec hardware in optimal mode



Update class H controller registers to configure codec in optimal mode.

CRs-fixed: 506099
Change-Id: I26ec0ad04bcec511ea2a37d2e357bae0345bd2a1
Signed-off-by: default avatarBhalchandra Gajare <gajare@codeaurora.org>
parent 5b6a0c3a
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+5 −4
Original line number Diff line number Diff line
@@ -6022,6 +6022,10 @@ static const struct wcd9xxx_reg_mask_val taiko_reg_defaults[] = {

	/* Set HPH Path to low power mode */
	TAIKO_REG_VAL(TAIKO_A_RX_HPH_BIAS_PA, 0x55),

	/* BUCK default */
	TAIKO_REG_VAL(WCD9XXX_A_BUCK_CTRL_CCL_4, 0x51),
	TAIKO_REG_VAL(WCD9XXX_A_BUCK_CTRL_CCL_1, 0x5B),
};

static const struct wcd9xxx_reg_mask_val taiko_1_0_reg_defaults[] = {
@@ -6030,13 +6034,9 @@ static const struct wcd9xxx_reg_mask_val taiko_1_0_reg_defaults[] = {
	 * Taiko 2.0 will have appropriate defaults for these registers.
	 */

	/* BUCK default */
	TAIKO_REG_VAL(WCD9XXX_A_BUCK_CTRL_CCL_4, 0x50),

	/* Required defaults for class H operation */
	TAIKO_REG_VAL(TAIKO_A_RX_HPH_CHOP_CTL, 0xF4),
	TAIKO_REG_VAL(TAIKO_A_BIAS_CURR_CTL_2, 0x08),
	TAIKO_REG_VAL(WCD9XXX_A_BUCK_CTRL_CCL_1, 0x5B),
	TAIKO_REG_VAL(WCD9XXX_A_BUCK_CTRL_CCL_3, 0x60),

	/* Choose max non-overlap time for NCP */
@@ -6128,6 +6128,7 @@ static const struct wcd9xxx_reg_mask_val taiko_2_0_reg_defaults[] = {
	TAIKO_REG_VAL(TAIKO_A_CDC_SPKR_CLIPDET_B1_CTL, 0x0),
	TAIKO_REG_VAL(TAIKO_A_CDC_COMP0_B4_CTL, 0x37),
	TAIKO_REG_VAL(TAIKO_A_CDC_COMP0_B5_CTL, 0x7f),
	TAIKO_REG_VAL(TAIKO_A_CDC_COMP0_B5_CTL, 0x7f),
};

static void taiko_update_reg_defaults(struct snd_soc_codec *codec)
+19 −31
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@

#define BUCK_VREF_0P494V 0x3F
#define BUCK_VREF_2V 0xFF
#define BUCK_VREF_0P494V 0x3F
#define BUCK_VREF_1P8V 0xE6

#define BUCK_SETTLE_TIME_US 50
@@ -414,12 +415,14 @@ static const struct wcd9xxx_imped_val imped_index[] = {

static inline void
wcd9xxx_enable_clsh_block(struct snd_soc_codec *codec,
			  struct wcd9xxx_clsh_cdc_data *clsh_d, bool on)
			  struct wcd9xxx_clsh_cdc_data *clsh_d, bool enable)
{
	if ((on && clsh_d->clsh_users++ == 1) ||
	    (!on && clsh_d->clsh_users-- == 0))
	if ((enable && ++clsh_d->clsh_users == 1) ||
	    (!enable && --clsh_d->clsh_users == 0))
		snd_soc_update_bits(codec, WCD9XXX_A_CDC_CLSH_B1_CTL,
				    0x01, on ? 0x01 : 0x00);
				    0x01, enable ? 0x01 : 0x00);
	dev_dbg(codec->dev, "%s: clsh_users %d, enable %d", __func__,
		clsh_d->clsh_users, enable);
}

static inline void wcd9xxx_enable_anc_delay(
@@ -432,12 +435,14 @@ static inline void wcd9xxx_enable_anc_delay(

static inline void
wcd9xxx_enable_buck(struct snd_soc_codec *codec,
		    struct wcd9xxx_clsh_cdc_data *clsh_d, bool on)
		    struct wcd9xxx_clsh_cdc_data *clsh_d, bool enable)
{
	if ((on && clsh_d->buck_users++ == 1) ||
	    (!on && clsh_d->buck_users-- == 0))
	if ((enable && ++clsh_d->buck_users == 1) ||
	    (!enable && --clsh_d->buck_users == 0))
		snd_soc_update_bits(codec, WCD9XXX_A_BUCK_MODE_1,
				    0x80, on ? 0x80 : 0x00);
				    0x80, enable ? 0x80 : 0x00);
	dev_dbg(codec->dev, "%s: buck_users %d, enable %d", __func__,
		clsh_d->buck_users, enable);
}

static void (*clsh_state_fp[NUM_CLSH_STATES])(struct snd_soc_codec *,
@@ -480,21 +485,6 @@ done:
	return buf;
}

static void wcd9xxx_cfg_clsh_buck(
		struct snd_soc_codec *codec)
{
	int i;
	const struct wcd9xxx_reg_mask_val reg_set[] = {
		{WCD9XXX_A_BUCK_CTRL_CCL_1, 0xF0, 0x50},
	};

	for (i = 0; i < ARRAY_SIZE(reg_set); i++)
		snd_soc_update_bits(codec, reg_set[i].reg, reg_set[i].mask,
						    reg_set[i].val);

	dev_dbg(codec->dev, "%s: Programmed buck parameters", __func__);
}

static void wcd9xxx_cfg_clsh_param_common(
		struct snd_soc_codec *codec)
{
@@ -665,7 +655,7 @@ static void wcd9xxx_set_buck_mode(struct snd_soc_codec *codec, u8 buck_vref)
{
	int i;
	const struct wcd9xxx_reg_mask_val reg_set[] = {
		{WCD9XXX_A_BUCK_MODE_5, 0x02, 0x03},
		{WCD9XXX_A_BUCK_MODE_5, 0x02, 0x02},
		{WCD9XXX_A_BUCK_MODE_4, 0xFF, buck_vref},
		{WCD9XXX_A_BUCK_MODE_1, 0x04, 0x04},
		{WCD9XXX_A_BUCK_MODE_3, 0x04, 0x00},
@@ -823,7 +813,6 @@ static void wcd9xxx_clsh_state_ear(struct snd_soc_codec *codec,
{
	pr_debug("%s: enter %s\n", __func__, is_enable ? "enable" : "disable");
	if (is_enable) {
		wcd9xxx_cfg_clsh_buck(codec);
		wcd9xxx_cfg_clsh_param_common(codec);
		wcd9xxx_cfg_clsh_param_ear(codec);
		wcd9xxx_enable_clsh_block(codec, clsh_d, true);
@@ -852,7 +841,6 @@ static void wcd9xxx_clsh_state_hph_l(struct snd_soc_codec *codec,
	pr_debug("%s: enter %s\n", __func__, is_enable ? "enable" : "disable");

	if (is_enable) {
		wcd9xxx_cfg_clsh_buck(codec);
		wcd9xxx_cfg_clsh_param_common(codec);
		wcd9xxx_cfg_clsh_param_hph(codec);
		wcd9xxx_enable_clsh_block(codec, clsh_d, true);
@@ -880,7 +868,6 @@ static void wcd9xxx_clsh_state_hph_r(struct snd_soc_codec *codec,
	pr_debug("%s: enter %s\n", __func__, is_enable ? "enable" : "disable");

	if (is_enable) {
		wcd9xxx_cfg_clsh_buck(codec);
		wcd9xxx_cfg_clsh_param_common(codec);
		wcd9xxx_cfg_clsh_param_hph(codec);
		wcd9xxx_enable_clsh_block(codec, clsh_d, true);
@@ -919,7 +906,8 @@ static void wcd9xxx_clsh_state_lo(struct snd_soc_codec *codec,
		struct wcd9xxx_clsh_cdc_data *clsh_d,
		u8 req_state, bool is_enable)
{
	pr_debug("%s: enter %s\n", __func__, is_enable ? "enable" : "disable");
	pr_debug("%s: enter %s, buck_mv %d\n", __func__,
		 is_enable ? "enable" : "disable", clsh_d->buck_mv);

	if (is_enable) {
		wcd9xxx_set_buck_mode(codec, BUCK_VREF_1P8V);
@@ -938,9 +926,9 @@ static void wcd9xxx_clsh_state_lo(struct snd_soc_codec *codec,
			usleep_range(NCP_SETTLE_TIME_US,
				     NCP_SETTLE_TIME_US + 10);
			snd_soc_update_bits(codec, WCD9XXX_A_BUCK_MODE_5,
					    0x01, 0x01);
					    0x01, (0x01 & 0x03));
			snd_soc_update_bits(codec, WCD9XXX_A_BUCK_MODE_5,
					    0xFB, (0x02 << 2));
					    0xFC, (0xFC & 0xB));
		}
		snd_soc_update_bits(codec, WCD9XXX_A_BUCK_MODE_1, 0x04, 0x00);
	} else {