Loading arch/arm/boot/dts/qcom/msm8916-qrd-skut1.dtsi +39 −0 Original line number Diff line number Diff line Loading @@ -12,3 +12,42 @@ */ #include "msm8916-qrd.dtsi" #include "dsi-panel-nt35521-wxga-video.dtsi" &mdss_mdp { qcom,mdss-pref-prim-intf = "dsi"; }; &pmx_mdss { qcom,num-grp-pins = <2>; qcom,pins = <&gp 8>, <&gp 25>; }; &mdss_dsi0 { qcom,dsi-pref-prim-pan = <&dsi_nt35521_wxga_video>; pinctrl-names = "mdss_default", "mdss_sleep"; pinctrl-0 = <&mdss_dsi_active>; pinctrl-1 = <&mdss_dsi_suspend>; qcom,platform-enable-gpio = <&msm_gpio 8 0>; qcom,platform-reset-gpio = <&msm_gpio 25 0>; }; &dsi_nt35521_wxga_video { qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; qcom,mdss-dsi-bl-pmic-pwm-frequency = <100>; qcom,mdss-dsi-bl-pmic-bank-select = <0>; qcom,mdss-dsi-pwm-gpio = <&pm8916_mpps 4 0>; qcom,cont-splash-enabled; }; &pm8916_mpps { mpp@a300 { /* MPP 4 */ /* Backlight PWM */ qcom,mode = <1>; /* Digital output */ qcom,invert = <0>; /* Disable invert */ qcom,src-sel = <4>; /* DTEST1 */ qcom,vin-sel = <0>; /* VPH_PWR */ qcom,master-en = <1>; /* Enable MPP */ }; }; Loading
arch/arm/boot/dts/qcom/msm8916-qrd-skut1.dtsi +39 −0 Original line number Diff line number Diff line Loading @@ -12,3 +12,42 @@ */ #include "msm8916-qrd.dtsi" #include "dsi-panel-nt35521-wxga-video.dtsi" &mdss_mdp { qcom,mdss-pref-prim-intf = "dsi"; }; &pmx_mdss { qcom,num-grp-pins = <2>; qcom,pins = <&gp 8>, <&gp 25>; }; &mdss_dsi0 { qcom,dsi-pref-prim-pan = <&dsi_nt35521_wxga_video>; pinctrl-names = "mdss_default", "mdss_sleep"; pinctrl-0 = <&mdss_dsi_active>; pinctrl-1 = <&mdss_dsi_suspend>; qcom,platform-enable-gpio = <&msm_gpio 8 0>; qcom,platform-reset-gpio = <&msm_gpio 25 0>; }; &dsi_nt35521_wxga_video { qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; qcom,mdss-dsi-bl-pmic-pwm-frequency = <100>; qcom,mdss-dsi-bl-pmic-bank-select = <0>; qcom,mdss-dsi-pwm-gpio = <&pm8916_mpps 4 0>; qcom,cont-splash-enabled; }; &pm8916_mpps { mpp@a300 { /* MPP 4 */ /* Backlight PWM */ qcom,mode = <1>; /* Digital output */ qcom,invert = <0>; /* Disable invert */ qcom,src-sel = <4>; /* DTEST1 */ qcom,vin-sel = <0>; /* VPH_PWR */ qcom,master-en = <1>; /* Enable MPP */ }; };