Loading drivers/tty/serial/msm_serial_hs.c +39 −3 Original line number Diff line number Diff line Loading @@ -1140,6 +1140,8 @@ static void msm_hs_set_termios(struct uart_port *uport, data = msm_hs_read(uport, UART_DM_MR1); data &= ~UARTDM_MR1_RX_RDY_CTL_BMSK; msm_hs_write(uport, UART_DM_MR1, data); /* set RFR_N to high */ msm_hs_write(uport, UART_DM_CR, RFR_HIGH); /* * Disable Rx channel of UARTDM Loading Loading @@ -1270,12 +1272,12 @@ static void msm_hs_set_termios(struct uart_port *uport, * UART Core would trigger RFR if it is not having any space with * RX FIFO. */ /* Pulling RFR line high */ msm_hs_write(uport, UART_DM_CR, RFR_LOW); data = msm_hs_read(uport, UART_DM_MR1); data &= ~(UARTDM_MR1_CTS_CTL_BMSK | UARTDM_MR1_RX_RDY_CTL_BMSK); if (c_cflag & CRTSCTS) { data |= UARTDM_MR1_CTS_CTL_BMSK; data |= UARTDM_MR1_RX_RDY_CTL_BMSK; } msm_hs_write(uport, UART_DM_MR1, data); msm_hs_write(uport, UART_DM_IMR, msm_uport->imr_reg); Loading Loading @@ -2086,6 +2088,7 @@ static int msm_hs_check_clock_off(struct uart_port *uport) { unsigned long sr_status; unsigned long flags; unsigned int data; struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); struct circ_buf *tx_buf = &uport->state->xmit; Loading @@ -2101,8 +2104,16 @@ static int msm_hs_check_clock_off(struct uart_port *uport) msm_uport->imr_reg & UARTDM_ISR_TXLEV_BMSK) { spin_unlock_irqrestore(&uport->lock, flags); mutex_unlock(&msm_uport->clk_mutex); if (msm_uport->clk_state == MSM_HS_CLK_REQUEST_OFF) if (msm_uport->clk_state == MSM_HS_CLK_REQUEST_OFF) { msm_uport->clk_state = MSM_HS_CLK_ON; /* Pulling RFR line high */ msm_hs_write(uport, UART_DM_CR, RFR_LOW); /* Enable auto RFR */ data = msm_hs_read(uport, UART_DM_MR1); data |= UARTDM_MR1_RX_RDY_CTL_BMSK; msm_hs_write(uport, UART_DM_MR1, data); mb(); } MSM_HS_DBG("%s(): clkstate %d", __func__, msm_uport->clk_state); return -1; } Loading Loading @@ -2134,6 +2145,14 @@ static int msm_hs_check_clock_off(struct uart_port *uport) spin_unlock_irqrestore(&uport->lock, flags); /* Pulling RFR line high */ msm_hs_write(uport, UART_DM_CR, RFR_LOW); /* Enable auto RFR */ data = msm_hs_read(uport, UART_DM_MR1); data |= UARTDM_MR1_RX_RDY_CTL_BMSK; msm_hs_write(uport, UART_DM_MR1, data); mb(); /* we really want to clock off */ msm_hs_clock_unvote(msm_uport); Loading Loading @@ -2308,6 +2327,14 @@ void msm_hs_request_clock_off(struct uart_port *uport) { spin_lock_irqsave(&uport->lock, flags); if (msm_uport->clk_state == MSM_HS_CLK_ON) { msm_uport->clk_state = MSM_HS_CLK_REQUEST_OFF; data = msm_hs_read(uport, UART_DM_MR1); /*disable auto ready-for-receiving */ data &= ~UARTDM_MR1_RX_RDY_CTL_BMSK; msm_hs_write(uport, UART_DM_MR1, data); mb(); /* set RFR_N to high */ msm_hs_write(uport, UART_DM_CR, RFR_HIGH); data = msm_hs_read(uport, UART_DM_SR); MSM_HS_DBG("%s(): TXEMT, queuing clock off work\n", __func__); Loading @@ -2329,6 +2356,15 @@ void msm_hs_request_clock_on(struct uart_port *uport) mutex_lock(&msm_uport->clk_mutex); spin_lock_irqsave(&uport->lock, flags); if (msm_uport->clk_state == MSM_HS_CLK_REQUEST_OFF) { /* Pulling RFR line high */ msm_hs_write(uport, UART_DM_CR, RFR_LOW); /* Enable auto RFR */ data = msm_hs_read(uport, UART_DM_MR1); data |= UARTDM_MR1_RX_RDY_CTL_BMSK; msm_hs_write(uport, UART_DM_MR1, data); mb(); } switch (msm_uport->clk_state) { case MSM_HS_CLK_OFF: wake_lock(&msm_uport->dma_wake_lock); Loading Loading
drivers/tty/serial/msm_serial_hs.c +39 −3 Original line number Diff line number Diff line Loading @@ -1140,6 +1140,8 @@ static void msm_hs_set_termios(struct uart_port *uport, data = msm_hs_read(uport, UART_DM_MR1); data &= ~UARTDM_MR1_RX_RDY_CTL_BMSK; msm_hs_write(uport, UART_DM_MR1, data); /* set RFR_N to high */ msm_hs_write(uport, UART_DM_CR, RFR_HIGH); /* * Disable Rx channel of UARTDM Loading Loading @@ -1270,12 +1272,12 @@ static void msm_hs_set_termios(struct uart_port *uport, * UART Core would trigger RFR if it is not having any space with * RX FIFO. */ /* Pulling RFR line high */ msm_hs_write(uport, UART_DM_CR, RFR_LOW); data = msm_hs_read(uport, UART_DM_MR1); data &= ~(UARTDM_MR1_CTS_CTL_BMSK | UARTDM_MR1_RX_RDY_CTL_BMSK); if (c_cflag & CRTSCTS) { data |= UARTDM_MR1_CTS_CTL_BMSK; data |= UARTDM_MR1_RX_RDY_CTL_BMSK; } msm_hs_write(uport, UART_DM_MR1, data); msm_hs_write(uport, UART_DM_IMR, msm_uport->imr_reg); Loading Loading @@ -2086,6 +2088,7 @@ static int msm_hs_check_clock_off(struct uart_port *uport) { unsigned long sr_status; unsigned long flags; unsigned int data; struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); struct circ_buf *tx_buf = &uport->state->xmit; Loading @@ -2101,8 +2104,16 @@ static int msm_hs_check_clock_off(struct uart_port *uport) msm_uport->imr_reg & UARTDM_ISR_TXLEV_BMSK) { spin_unlock_irqrestore(&uport->lock, flags); mutex_unlock(&msm_uport->clk_mutex); if (msm_uport->clk_state == MSM_HS_CLK_REQUEST_OFF) if (msm_uport->clk_state == MSM_HS_CLK_REQUEST_OFF) { msm_uport->clk_state = MSM_HS_CLK_ON; /* Pulling RFR line high */ msm_hs_write(uport, UART_DM_CR, RFR_LOW); /* Enable auto RFR */ data = msm_hs_read(uport, UART_DM_MR1); data |= UARTDM_MR1_RX_RDY_CTL_BMSK; msm_hs_write(uport, UART_DM_MR1, data); mb(); } MSM_HS_DBG("%s(): clkstate %d", __func__, msm_uport->clk_state); return -1; } Loading Loading @@ -2134,6 +2145,14 @@ static int msm_hs_check_clock_off(struct uart_port *uport) spin_unlock_irqrestore(&uport->lock, flags); /* Pulling RFR line high */ msm_hs_write(uport, UART_DM_CR, RFR_LOW); /* Enable auto RFR */ data = msm_hs_read(uport, UART_DM_MR1); data |= UARTDM_MR1_RX_RDY_CTL_BMSK; msm_hs_write(uport, UART_DM_MR1, data); mb(); /* we really want to clock off */ msm_hs_clock_unvote(msm_uport); Loading Loading @@ -2308,6 +2327,14 @@ void msm_hs_request_clock_off(struct uart_port *uport) { spin_lock_irqsave(&uport->lock, flags); if (msm_uport->clk_state == MSM_HS_CLK_ON) { msm_uport->clk_state = MSM_HS_CLK_REQUEST_OFF; data = msm_hs_read(uport, UART_DM_MR1); /*disable auto ready-for-receiving */ data &= ~UARTDM_MR1_RX_RDY_CTL_BMSK; msm_hs_write(uport, UART_DM_MR1, data); mb(); /* set RFR_N to high */ msm_hs_write(uport, UART_DM_CR, RFR_HIGH); data = msm_hs_read(uport, UART_DM_SR); MSM_HS_DBG("%s(): TXEMT, queuing clock off work\n", __func__); Loading @@ -2329,6 +2356,15 @@ void msm_hs_request_clock_on(struct uart_port *uport) mutex_lock(&msm_uport->clk_mutex); spin_lock_irqsave(&uport->lock, flags); if (msm_uport->clk_state == MSM_HS_CLK_REQUEST_OFF) { /* Pulling RFR line high */ msm_hs_write(uport, UART_DM_CR, RFR_LOW); /* Enable auto RFR */ data = msm_hs_read(uport, UART_DM_MR1); data |= UARTDM_MR1_RX_RDY_CTL_BMSK; msm_hs_write(uport, UART_DM_MR1, data); mb(); } switch (msm_uport->clk_state) { case MSM_HS_CLK_OFF: wake_lock(&msm_uport->dma_wake_lock); Loading