Loading arch/arm/mach-msm/pcie_phy.c +3 −1 Original line number Diff line number Diff line Loading @@ -89,9 +89,11 @@ void pcie_phy_init(struct msm_pcie_dev_t *dev) write_phy(dev->phy, QSERDES_RX_CDR_CONTROL1, 0xF3); write_phy(dev->phy, QSERDES_RX_CDR_CONTROL_HALF, 0x2B); write_phy(dev->phy, QSERDES_COM_PLL_VCOTAIL_EN, 0xE1); /* Calibration Settings */ write_phy(dev->phy, QSERDES_COM_RESETSM_CNTRL, 0x90); write_phy(dev->phy, QSERDES_COM_RESETSM_CNTRL2, 0x05); write_phy(dev->phy, QSERDES_COM_RESETSM_CNTRL2, 0x7); /* Additional writes */ write_phy(dev->phy, QSERDES_COM_RES_CODE_START_SEG1, 0x20); Loading Loading
arch/arm/mach-msm/pcie_phy.c +3 −1 Original line number Diff line number Diff line Loading @@ -89,9 +89,11 @@ void pcie_phy_init(struct msm_pcie_dev_t *dev) write_phy(dev->phy, QSERDES_RX_CDR_CONTROL1, 0xF3); write_phy(dev->phy, QSERDES_RX_CDR_CONTROL_HALF, 0x2B); write_phy(dev->phy, QSERDES_COM_PLL_VCOTAIL_EN, 0xE1); /* Calibration Settings */ write_phy(dev->phy, QSERDES_COM_RESETSM_CNTRL, 0x90); write_phy(dev->phy, QSERDES_COM_RESETSM_CNTRL2, 0x05); write_phy(dev->phy, QSERDES_COM_RESETSM_CNTRL2, 0x7); /* Additional writes */ write_phy(dev->phy, QSERDES_COM_RES_CODE_START_SEG1, 0x20); Loading