Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 28f078a5 authored by Kalyan Thota's avatar Kalyan Thota
Browse files

msm: mdss: handle WB2 irq for MDSS 1.8.0 



In MDSS 1.8.0, bit 2 in intr enable and intr status register
is marked for WB2 which is different from the other targets.
Add changes to handle the same.

Change-Id: I76947bc218c897e121bb22fbda7aaa57723ec708
Signed-off-by: default avatarKalyan Thota <kalyant@codeaurora.org>
parent 239c5a38

drivers/video/msm/mdss/mdss_mdp_intf_writeback.c

+6 −0
Original line number Diff line number Diff line
@@ -565,6 +565,12 @@ int mdss_mdp_writeback_start(struct mdss_mdp_ctl *ctl) 
	spin_lock_init(&ctx->wb_lock);

	INIT_LIST_HEAD(&ctx->vsync_handlers);



	/* WB2 Intr Enable is BIT(2) in MDSS 1.8.0 */

	if (ctl->mdata->mdp_rev == MDSS_MDP_HW_REV_108) {

		ctx->intr_type = MDSS_MDP_IRQ_WB_ROT_COMP;

		ctx->intf_num = 2;

	}



	if (ctx->type == MDSS_MDP_WRITEBACK_TYPE_ROTATOR)

		ctl->prepare_fnc = mdss_mdp_writeback_prepare_rot;

	else /* wfd or line mode */

drivers/video/msm/mdss/mdss_mdp_util.c

+2 −1
Original line number Diff line number Diff line
@@ -211,7 +211,8 @@ irqreturn_t mdss_mdp_isr(int irq, void *ptr) 
		mdss_misr_crc_collect(mdata, DISPLAY_MISR_MDP);

	}



	if (isr & MDSS_MDP_INTR_WB_2_DONE) {

	if (isr & ((mdata->mdp_rev == MDSS_MDP_HW_REV_108) ?

		MDSS_MDP_INTR_WB_2_DONE >> 2 : MDSS_MDP_INTR_WB_2_DONE)) {

		mdss_mdp_intr_done(MDP_INTR_WB_2);

		mdss_misr_crc_collect(mdata, DISPLAY_MISR_MDP);

	}