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Commit 28cfff9c authored by Naveen Kaje's avatar Naveen Kaje
Browse files

ARM: dts: msm: add HSUART configs for 8994 



Provide driver configs and pinctrl settings to enable
one High Speed UART core.

Change-Id: I1f18ffe49b9ac5effb3bbd02f4c7a2ef317862a5
Signed-off-by: default avatarNaveen Kaje <nkaje@codeaurora.org>
parent 28024c52

arch/arm/boot/dts/qcom/msm8994-pinctrl.dtsi

+22 −0
Original line number Diff line number Diff line
@@ -43,6 +43,28 @@ 
			};

		};



		blsp1_uart2_active {

			qcom,pins = <&gp 4>, <&gp 5>, <&gp 6>, <&gp 7>;

			qcom,num-grp-pins = <4>;

			qcom,pin-func = <2>;

		        label = "blsp1_uart2_active";

			hsuart_active: default {

				drive-strength = <16>;

				bias-disable;

			};

		};



		blsp1_uart2_sleep {

			qcom,pins = <&gp 4>, <&gp 5>, <&gp 6>, <&gp 7>;

			qcom,num-grp-pins = <4>;

			qcom,pin-func = <0>;

		        label = "blsp1_uart2_sleep";

			hsuart_sleep: sleep {

				drive-strength = <2>;

				bias-disable;

			};

		};



		spi_0 {

			qcom,pins = <&gp 0>, <&gp 1>, <&gp 3>;

			qcom,num-grp-pins = <3>;

arch/arm/boot/dts/qcom/msm8994-sim.dts

+4 −0
Original line number Diff line number Diff line
@@ -233,3 +233,7 @@ 
	qcom,use-non-secure-pil;

	qcom,fw-bias = <0xf500000>;

};



&blsp1_uart2 {

	status = "ok";

};

arch/arm/boot/dts/qcom/msm8994.dtsi

+34 −0
Original line number Diff line number Diff line
@@ -186,6 +186,40 @@ 
			<&clock_gcc clk_gcc_blsp1_ahb_clk>;

	};



	blsp1_uart2: uart@f991e000 { /* BLSP1 UART2 */

		compatible = "qcom,msm-hsuart-v14";

		reg = <0xf991e000 0x1000>,

			<0xf9904000 0x19000>;

		status = "disabled";

		reg-names = "core_mem", "bam_mem";

		interrupt-names = "core_irq", "bam_irq", "wakeup_irq";

		#address-cells = <0>;

		interrupt-parent = <&blsp1_uart2>;

		interrupts = <0 1 2>;

		#interrupt-cells = <1>;

		interrupt-map-mask = <0xffffffff>;

		interrupt-map = <0 &intc 0 108 0

				1 &intc 0 238 0

				2 &msm_gpio 5 0>;



		qcom,bam-tx-ep-pipe-index = <2>;

		qcom,bam-rx-ep-pipe-index = <3>;

		qcom,master-id = <86>;

		clock-names = "core_clk", "iface_clk";

		clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>,

			<&clock_gcc clk_gcc_blsp1_ahb_clk>;

		pinctrl-names = "sleep", "default";

		pinctrl-0 = <&hsuart_sleep>;

		pinctrl-1 = <&hsuart_active>;



		qcom,msm-bus,name = "buart5";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<86 512 0 0>,

				<86 512 500 800>;

	};



	qcom,sps@f9984000 {

		compatible = "qcom,msm_sps";

		reg-names = "bam_mem", "core_mem";