Loading drivers/video/msm/mdss/mdss_mdp_overlay.c +13 −5 Original line number Diff line number Diff line Loading @@ -397,7 +397,8 @@ static int __mdp_pipe_tune_perf(struct mdss_mdp_pipe *pipe) * mdp clock requirement */ if (mdata->has_decimation && (pipe->vert_deci < MAX_DECIMATION) && !pipe->bwc_mode && !pipe->src_fmt->tile) && !pipe->bwc_mode && !pipe->src_fmt->tile && !pipe->scale.enable_pxl_ext) pipe->vert_deci++; else return -EPERM; Loading Loading @@ -798,13 +799,20 @@ static int mdss_mdp_overlay_pipe_setup(struct msm_fb_data_type *mfd, } } if ((pipe->flags & MDP_DEINTERLACE) && !pipe->scale.enable_pxl_ext) { /* * When scaling is enabled src crop and image * width and height is modified by user */ if ((pipe->flags & MDP_DEINTERLACE)) { if (pipe->flags & MDP_SOURCE_ROTATED_90) { pipe->src.x = DIV_ROUND_UP(pipe->src.x, 2); pipe->src.x &= ~1; if (!pipe->scale.enable_pxl_ext) { pipe->src.w /= 2; pipe->img_width /= 2; } } else { if (!pipe->scale.enable_pxl_ext) pipe->src.h /= 2; pipe->src.y = DIV_ROUND_UP(pipe->src.y, 2); pipe->src.y &= ~1; Loading drivers/video/msm/mdss/mdss_mdp_pp.c +42 −30 Original line number Diff line number Diff line Loading @@ -1181,39 +1181,51 @@ static int mdss_mdp_scale_setup(struct mdss_mdp_pipe *pipe) } } if (pipe->scale.enable_pxl_ext && pipe->type == MDSS_MDP_PIPE_TYPE_VIG) { if (pipe->scale.enable_pxl_ext) { if (pipe->type == MDSS_MDP_PIPE_TYPE_VIG) { /*program x,y initial phase and phase step*/ writel_relaxed(pipe->scale.init_phase_x[0], pipe->base + MDSS_MDP_REG_VIG_QSEED2_C03_INIT_PHASEX); pipe->base + MDSS_MDP_REG_VIG_QSEED2_C03_INIT_PHASEX); writel_relaxed(pipe->scale.phase_step_x[0], pipe->base + MDSS_MDP_REG_VIG_QSEED2_C03_PHASESTEPX); pipe->base + MDSS_MDP_REG_VIG_QSEED2_C03_PHASESTEPX); writel_relaxed(pipe->scale.init_phase_x[1], pipe->base + MDSS_MDP_REG_VIG_QSEED2_C12_INIT_PHASEX); pipe->base + MDSS_MDP_REG_VIG_QSEED2_C12_INIT_PHASEX); writel_relaxed(pipe->scale.phase_step_x[1], pipe->base + MDSS_MDP_REG_VIG_QSEED2_C12_PHASESTEPX); pipe->base + MDSS_MDP_REG_VIG_QSEED2_C12_PHASESTEPX); writel_relaxed(pipe->scale.init_phase_y[0], pipe->base + MDSS_MDP_REG_VIG_QSEED2_C03_INIT_PHASEY); pipe->base + MDSS_MDP_REG_VIG_QSEED2_C03_INIT_PHASEY); writel_relaxed(pipe->scale.phase_step_y[0], pipe->base + MDSS_MDP_REG_VIG_QSEED2_C03_PHASESTEPY); pipe->base + MDSS_MDP_REG_VIG_QSEED2_C03_PHASESTEPY); writel_relaxed(pipe->scale.init_phase_y[1], pipe->base + MDSS_MDP_REG_VIG_QSEED2_C12_INIT_PHASEY); pipe->base + MDSS_MDP_REG_VIG_QSEED2_C12_INIT_PHASEY); writel_relaxed(pipe->scale.phase_step_y[1], pipe->base + MDSS_MDP_REG_VIG_QSEED2_C12_PHASESTEPY); pipe->base + MDSS_MDP_REG_VIG_QSEED2_C12_PHASESTEPY); } else { /*program pixel extn values for the SSPP*/ mdss_mdp_pipe_program_pixel_extn(pipe); } else if (pipe->type == MDSS_MDP_PIPE_TYPE_VIG) { writel_relaxed(phasex_step, pipe->base + writel_relaxed(pipe->scale.phase_step_x[0], pipe->base + MDSS_MDP_REG_SCALE_PHASE_STEP_X); writel_relaxed(phasey_step, pipe->base + writel_relaxed(pipe->scale.phase_step_y[0], pipe->base + MDSS_MDP_REG_SCALE_PHASE_STEP_Y); writel_relaxed(init_phasex, pipe->base + writel_relaxed(pipe->scale.init_phase_x[0], pipe->base + MDSS_MDP_REG_SCALE_INIT_PHASE_X); writel_relaxed(init_phasey, pipe->base + writel_relaxed(pipe->scale.init_phase_y[0], pipe->base + MDSS_MDP_REG_SCALE_INIT_PHASE_Y); } /*program pixel extn values for the SSPP*/ mdss_mdp_pipe_program_pixel_extn(pipe); } else { writel_relaxed(phasex_step, pipe->base + MDSS_MDP_REG_SCALE_PHASE_STEP_X); Loading Loading
drivers/video/msm/mdss/mdss_mdp_overlay.c +13 −5 Original line number Diff line number Diff line Loading @@ -397,7 +397,8 @@ static int __mdp_pipe_tune_perf(struct mdss_mdp_pipe *pipe) * mdp clock requirement */ if (mdata->has_decimation && (pipe->vert_deci < MAX_DECIMATION) && !pipe->bwc_mode && !pipe->src_fmt->tile) && !pipe->bwc_mode && !pipe->src_fmt->tile && !pipe->scale.enable_pxl_ext) pipe->vert_deci++; else return -EPERM; Loading Loading @@ -798,13 +799,20 @@ static int mdss_mdp_overlay_pipe_setup(struct msm_fb_data_type *mfd, } } if ((pipe->flags & MDP_DEINTERLACE) && !pipe->scale.enable_pxl_ext) { /* * When scaling is enabled src crop and image * width and height is modified by user */ if ((pipe->flags & MDP_DEINTERLACE)) { if (pipe->flags & MDP_SOURCE_ROTATED_90) { pipe->src.x = DIV_ROUND_UP(pipe->src.x, 2); pipe->src.x &= ~1; if (!pipe->scale.enable_pxl_ext) { pipe->src.w /= 2; pipe->img_width /= 2; } } else { if (!pipe->scale.enable_pxl_ext) pipe->src.h /= 2; pipe->src.y = DIV_ROUND_UP(pipe->src.y, 2); pipe->src.y &= ~1; Loading
drivers/video/msm/mdss/mdss_mdp_pp.c +42 −30 Original line number Diff line number Diff line Loading @@ -1181,39 +1181,51 @@ static int mdss_mdp_scale_setup(struct mdss_mdp_pipe *pipe) } } if (pipe->scale.enable_pxl_ext && pipe->type == MDSS_MDP_PIPE_TYPE_VIG) { if (pipe->scale.enable_pxl_ext) { if (pipe->type == MDSS_MDP_PIPE_TYPE_VIG) { /*program x,y initial phase and phase step*/ writel_relaxed(pipe->scale.init_phase_x[0], pipe->base + MDSS_MDP_REG_VIG_QSEED2_C03_INIT_PHASEX); pipe->base + MDSS_MDP_REG_VIG_QSEED2_C03_INIT_PHASEX); writel_relaxed(pipe->scale.phase_step_x[0], pipe->base + MDSS_MDP_REG_VIG_QSEED2_C03_PHASESTEPX); pipe->base + MDSS_MDP_REG_VIG_QSEED2_C03_PHASESTEPX); writel_relaxed(pipe->scale.init_phase_x[1], pipe->base + MDSS_MDP_REG_VIG_QSEED2_C12_INIT_PHASEX); pipe->base + MDSS_MDP_REG_VIG_QSEED2_C12_INIT_PHASEX); writel_relaxed(pipe->scale.phase_step_x[1], pipe->base + MDSS_MDP_REG_VIG_QSEED2_C12_PHASESTEPX); pipe->base + MDSS_MDP_REG_VIG_QSEED2_C12_PHASESTEPX); writel_relaxed(pipe->scale.init_phase_y[0], pipe->base + MDSS_MDP_REG_VIG_QSEED2_C03_INIT_PHASEY); pipe->base + MDSS_MDP_REG_VIG_QSEED2_C03_INIT_PHASEY); writel_relaxed(pipe->scale.phase_step_y[0], pipe->base + MDSS_MDP_REG_VIG_QSEED2_C03_PHASESTEPY); pipe->base + MDSS_MDP_REG_VIG_QSEED2_C03_PHASESTEPY); writel_relaxed(pipe->scale.init_phase_y[1], pipe->base + MDSS_MDP_REG_VIG_QSEED2_C12_INIT_PHASEY); pipe->base + MDSS_MDP_REG_VIG_QSEED2_C12_INIT_PHASEY); writel_relaxed(pipe->scale.phase_step_y[1], pipe->base + MDSS_MDP_REG_VIG_QSEED2_C12_PHASESTEPY); pipe->base + MDSS_MDP_REG_VIG_QSEED2_C12_PHASESTEPY); } else { /*program pixel extn values for the SSPP*/ mdss_mdp_pipe_program_pixel_extn(pipe); } else if (pipe->type == MDSS_MDP_PIPE_TYPE_VIG) { writel_relaxed(phasex_step, pipe->base + writel_relaxed(pipe->scale.phase_step_x[0], pipe->base + MDSS_MDP_REG_SCALE_PHASE_STEP_X); writel_relaxed(phasey_step, pipe->base + writel_relaxed(pipe->scale.phase_step_y[0], pipe->base + MDSS_MDP_REG_SCALE_PHASE_STEP_Y); writel_relaxed(init_phasex, pipe->base + writel_relaxed(pipe->scale.init_phase_x[0], pipe->base + MDSS_MDP_REG_SCALE_INIT_PHASE_X); writel_relaxed(init_phasey, pipe->base + writel_relaxed(pipe->scale.init_phase_y[0], pipe->base + MDSS_MDP_REG_SCALE_INIT_PHASE_Y); } /*program pixel extn values for the SSPP*/ mdss_mdp_pipe_program_pixel_extn(pipe); } else { writel_relaxed(phasex_step, pipe->base + MDSS_MDP_REG_SCALE_PHASE_STEP_X); Loading