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Commit 27b2f679 authored Sep 16, 2005 by Adam Kropelin Committed by Linus Torvalds Sep 17, 2005

[PATCH] qla2xxx: Use dword accessors for PCI_ROM_ADDRESS



PCI_ROM_ADDRESS is a 32 bit register and as such should be accessed using
pci_bus_{read,write}_config_dword().  A recent audit of drivers/ turned up
several cases of byte- and word-sized accesses.  The harmful ones were fixed
by Linus directly.  This patches up one of the remaining
harmless-but-still-wrong cases caught in the dragnet.

Signed-off-by: Adam Kropelin <akropel1@rochester.rr.com>
Cc: Andrew Vasquez <andrew.vasquez@qlogic.com>
Cc: Greg KH <greg@kroah.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

parent 06c6d271

drivers/scsi/qla2xxx/qla_init.c

+12 −9

Original line number	Original line	Diff line number	Diff line
	@@ -201,6 +201,7 @@ int
	qla2100_pci_config(scsi_qla_host_t *ha)		qla2100_pci_config(scsi_qla_host_t *ha)
	{		{
	uint16_t w, mwi;		uint16_t w, mwi;
			uint32_t d;
	unsigned long flags;		unsigned long flags;
	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;		struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;

	@@ -215,9 +216,9 @@ qla2100_pci_config(scsi_qla_host_t *ha)
	pci_write_config_word(ha->pdev, PCI_COMMAND, w);		pci_write_config_word(ha->pdev, PCI_COMMAND, w);

	/* Reset expansion ROM address decode enable */		/* Reset expansion ROM address decode enable */
	pci_read_config_word(ha->pdev, PCI_ROM_ADDRESS, &w);		pci_read_config_dword(ha->pdev, PCI_ROM_ADDRESS, &d);
	w &= ~PCI_ROM_ADDRESS_ENABLE;		d &= ~PCI_ROM_ADDRESS_ENABLE;
	pci_write_config_word(ha->pdev, PCI_ROM_ADDRESS, w);		pci_write_config_dword(ha->pdev, PCI_ROM_ADDRESS, d);

	/* Get PCI bus information. */		/* Get PCI bus information. */
	spin_lock_irqsave(&ha->hardware_lock, flags);		spin_lock_irqsave(&ha->hardware_lock, flags);
	@@ -237,6 +238,7 @@ int
	qla2300_pci_config(scsi_qla_host_t *ha)		qla2300_pci_config(scsi_qla_host_t *ha)
	{		{
	uint16_t w, mwi;		uint16_t w, mwi;
			uint32_t d;
	unsigned long flags = 0;		unsigned long flags = 0;
	uint32_t cnt;		uint32_t cnt;
	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;		struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
	@@ -302,9 +304,9 @@ qla2300_pci_config(scsi_qla_host_t *ha)
	pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);		pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);

	/* Reset expansion ROM address decode enable */		/* Reset expansion ROM address decode enable */
	pci_read_config_word(ha->pdev, PCI_ROM_ADDRESS, &w);		pci_read_config_dword(ha->pdev, PCI_ROM_ADDRESS, &d);
	w &= ~PCI_ROM_ADDRESS_ENABLE;		d &= ~PCI_ROM_ADDRESS_ENABLE;
	pci_write_config_word(ha->pdev, PCI_ROM_ADDRESS, w);		pci_write_config_dword(ha->pdev, PCI_ROM_ADDRESS, d);

	/* Get PCI bus information. */		/* Get PCI bus information. */
	spin_lock_irqsave(&ha->hardware_lock, flags);		spin_lock_irqsave(&ha->hardware_lock, flags);
	@@ -324,6 +326,7 @@ int
	qla24xx_pci_config(scsi_qla_host_t *ha)		qla24xx_pci_config(scsi_qla_host_t *ha)
	{		{
	uint16_t w, mwi;		uint16_t w, mwi;
			uint32_t d;
	unsigned long flags = 0;		unsigned long flags = 0;
	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;		struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
	int pcix_cmd_reg, pcie_dctl_reg;		int pcix_cmd_reg, pcie_dctl_reg;
	@@ -366,9 +369,9 @@ qla24xx_pci_config(scsi_qla_host_t *ha)
	}		}

	/* Reset expansion ROM address decode enable */		/* Reset expansion ROM address decode enable */
	pci_read_config_word(ha->pdev, PCI_ROM_ADDRESS, &w);		pci_read_config_dword(ha->pdev, PCI_ROM_ADDRESS, &d);
	w &= ~PCI_ROM_ADDRESS_ENABLE;		d &= ~PCI_ROM_ADDRESS_ENABLE;
	pci_write_config_word(ha->pdev, PCI_ROM_ADDRESS, w);		pci_write_config_dword(ha->pdev, PCI_ROM_ADDRESS, d);

	/* Get PCI bus information. */		/* Get PCI bus information. */
	spin_lock_irqsave(&ha->hardware_lock, flags);		spin_lock_irqsave(&ha->hardware_lock, flags);