Commit 25f24528 authored Jun 05, 2014 by Mayank Rana

ARM: dts: mdm9630: Provide PERIPH_SS_AHB2PHY register address



Prior to initializing the QMP PHY, it is recommended to configure
the AHB2PHY bridge to operate with one wait state reads and writes.
Hence provide PERIPH_SS_AHB2PHY_TOP_CFG register address to
configure this functionality.

Change-Id: I999750be3435500c848426416e85a9fbd2643cb1
Signed-off-by: Mayank Rana <mrana@codeaurora.org>

parent b5a909ab

arch/arm/boot/dts/qcom/mdm9630.dtsi

+2 −1

Original line number	Diff line number	Diff line
		@@ -538,7 +538,8 @@

		ssphy0: ssphy@f9b38000 {
		compatible = "qcom,usb-ssphy-qmp";
		reg = <0xf9b38000 0x16c>;
		reg = <0xf9b38000 0x16c>,
		<0xf9b3e000 0x3ff>;
		vdd-supply = <&pmd9635_l4>;
		vdda18-supply = <&pmd9635_l8>;
		qcom,vdd-voltage-level = <0 900000 1050000>;