clk: mdss: fix PLL locking issues for 8994 DSI PHY

Not all PLL registers are reset to default values when
VCO frequency is changed without doing PHY reset. Configure
the needed registers in init_lock sequence to avoid PLL
lock failures.

Change-Id: I273797ac8cbfae69027571972518eb2665b21423
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>