Merge "ARM: dts: msm: add coresight components for msmferrum"

/* Copyright (c) 2014, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */

&soc {

	tmc_etr: tmc@826000 {

		compatible = "arm,coresight-tmc";

		reg = <0x826000 0x1000>,

		      <0x884000 0x15000>;

		reg-names = "tmc-base", "bam-base";

		qcom,memory-size = <0x100000>;

		coresight-id = <0>;

		coresight-name = "coresight-tmc-etr";

		coresight-nr-inports = <1>;

		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};

	replicator: replicator@824000 {

		compatible = "qcom,coresight-replicator";

		reg = <0x824000 0x1000>;

		reg-names = "replicator-base";

		coresight-id = <1>;

		coresight-name = "coresight-replicator";

		coresight-nr-inports = <1>;

		coresight-outports = <0>;

		coresight-child-list = <&tmc_etr>;

		coresight-child-ports = <0>;

		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};

	tmc_etf: tmc@825000 {

		compatible = "arm,coresight-tmc";

		reg = <0x825000 0x1000>;

		reg-names = "tmc-base";

		coresight-id = <2>;

		coresight-name = "coresight-tmc-etf";

		coresight-nr-inports = <1>;

		coresight-outports = <0>;

		coresight-child-list = <&replicator>;

		coresight-child-ports = <0>;

		coresight-default-sink;

		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};

	funnel_in0: funnel@821000 {

		compatible = "arm,coresight-funnel";

		reg = <0x821000 0x1000>;

		reg-names = "funnel-base";

		coresight-id = <3>;

		coresight-name = "coresight-funnel-in0";

		coresight-nr-inports = <8>;

		coresight-outports = <0>;

		coresight-child-list = <&tmc_etf>;

		coresight-child-ports = <0>;

		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};

	stm: stm@802000 {

		compatible = "arm,coresight-stm";

		reg = <0x802000 0x1000>,

		      <0x9280000 0x180000>;

		reg-names = "stm-base", "stm-data-base";

		coresight-id = <4>;

		coresight-name = "coresight-stm";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_in0>;

		coresight-child-ports = <7>;

		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};

	csr: csr@801000 {

		compatible = "qcom,coresight-csr";

		reg = <0x801000 0x1000>;

		reg-names = "csr-base";

		coresight-id = <5>;

		coresight-name = "coresight-csr";

		coresight-nr-inports = <0>;

		qcom,blk-size = <1>;

		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};

};

#include "msm-gdsc-8916.dtsi"

#include "msmferrum-iommu.dtsi"

#include "msmferrum-gpu.dtsi"

#include "msmferrum-coresight.dtsi"

&soc {

	#address-cells = <1>;