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Commit 205282e9 authored by Jordan Crouse's avatar Jordan Crouse
Browse files

msm: kgsl: Make GPU core support more generic 



GPU device code has mostly congealed into place over time. Remove
some of the nastier workarounds and try to provide a consistant
method for accessing the GPU core specific functions and bits
and pieces located therein. Add more feature flags to avoid
if (adreno_is_XXX()) decision trees and try to not convert back
and forth between struct kgsl_device and struct adreno_device so
much.

Change-Id: Ic0dedbad3692f6d1f4db535ec74178203d3aab53
Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
parent 1d3124ad

drivers/gpu/msm/adreno-gpulist.h

+31 −78
Original line number Original line Diff line number Diff line
@@ -12,58 +12,17 @@ 
 */

 */





#define ANY_ID (~0)

#define ANY_ID (~0)

#define NO_VER (~0)





/**

static const struct adreno_gpu_core adreno_gpulist[] = {

 * struct adreno_gpudev - GPU device definition

 * @gpurev: Unique GPU revision identifier

 * @core: Match for the core version of the GPU

 * @major: Match for the major version of the GPU

 * @minor: Match for the minor version of the GPU

 * @patchid: Match for the patch revision of the GPU

 * @features: Common adreno features supported by this core

 * @pm4fw: Filename for th PM4 firmware

 * @pfpfw: Filename for the PFP firmware

 * @gpudev: Pointer to the GPU family specific functions for this core

 * @gmem_size: Amount of binning memory (GMEM/OCMEM) to reserve for the core

 * @sync_lock_pm4_ver: For IOMMUv0 cores the version of PM4 microcode that

 * supports the sync lock mechanism

 * @sync_lock_pfp_ver: For IOMMUv0 cores the version of PFP microcode that

 * supports the sync lock mechanism

 * @pm4_jt_idx: Index of the jump table in the PM4 microcode

 * @pm4_jt_addr: Address offset to load the jump table for the PM4 microcode

 * @pfp_jt_idx: Index of the jump table in the PFP microcode

 * @pfp_jt_addr: Address offset to load the jump table for the PFP microcode

 * @pm4_bstrp_size: Size of the bootstrap loader for PM4 microcode

 * @pfp_bstrp_size: Size of the bootstrap loader for PFP microcde

 * @pfp_bstrp_ver: Version of the PFP microcode that supports bootstraping

 */

static const struct adreno_gpulist {

	enum adreno_gpurev gpurev;

	unsigned int core, major, minor, patchid;

	unsigned long features;

	const char *pm4fw;

	const char *pfpfw;

	struct adreno_gpudev *gpudev;

	unsigned int gmem_size;

	unsigned int sync_lock_pm4_ver;

	unsigned int sync_lock_pfp_ver;

	unsigned int pm4_jt_idx;

	unsigned int pm4_jt_addr;

	unsigned int pfp_jt_idx;

	unsigned int pfp_jt_addr;

	unsigned int pm4_bstrp_size;

	unsigned int pfp_bstrp_size;

	unsigned int pfp_bstrp_ver;

} adreno_gpulist[] = {

	{

	{

		.gpurev = ADRENO_REV_A305,

		.gpurev = ADRENO_REV_A305,

		.core = 3,

		.core = 3,

		.major = 0,

		.major = 0,

		.minor = 5,

		.minor = 5,

		.patchid = 0,

		.patchid = 0,

		.pm4fw = "a300_pm4.fw",

		.features = ADRENO_HAS_IOMMU_SYNC_LOCK,

		.pfpfw = "a300_pfp.fw",

		.pm4fw_name = "a300_pm4.fw",

		.pfpfw_name = "a300_pfp.fw",

		.gpudev = &adreno_a3xx_gpudev,

		.gpudev = &adreno_a3xx_gpudev,

		.gmem_size = SZ_256K,

		.gmem_size = SZ_256K,

		.sync_lock_pm4_ver = 0x3FF037,

		.sync_lock_pm4_ver = 0x3FF037,
@@ -75,8 +34,9 @@ static const struct adreno_gpulist { 
		.major = 2,

		.major = 2,

		.minor = ANY_ID,

		.minor = ANY_ID,

		.patchid = ANY_ID,

		.patchid = ANY_ID,

		.pm4fw = "a300_pm4.fw",

		.features = ADRENO_HAS_IOMMU_SYNC_LOCK,

		.pfpfw = "a300_pfp.fw",

		.pm4fw_name = "a300_pm4.fw",

		.pfpfw_name = "a300_pfp.fw",

		.gpudev = &adreno_a3xx_gpudev,

		.gpudev = &adreno_a3xx_gpudev,

		.gmem_size = SZ_512K,

		.gmem_size = SZ_512K,

		.sync_lock_pm4_ver = 0x3FF037,

		.sync_lock_pm4_ver = 0x3FF037,
@@ -88,13 +48,12 @@ static const struct adreno_gpulist { 
		.major = 3,

		.major = 3,

		.minor = 0,

		.minor = 0,

		.patchid = ANY_ID,

		.patchid = ANY_ID,

		.features = ADRENO_USES_OCMEM | IOMMU_FLUSH_TLB_ON_MAP,

		.features = ADRENO_USES_OCMEM | IOMMU_FLUSH_TLB_ON_MAP |

		.pm4fw = "a330_pm4.fw",

			ADRENO_WARM_START | ADRENO_USE_BOOTSTRAP,

		.pfpfw = "a330_pfp.fw",

		.pm4fw_name = "a330_pm4.fw",

		.pfpfw_name = "a330_pfp.fw",

		.gpudev = &adreno_a3xx_gpudev,

		.gpudev = &adreno_a3xx_gpudev,

		.gmem_size = SZ_1M,

		.gmem_size = SZ_1M,

		.sync_lock_pm4_ver = NO_VER,

		.sync_lock_pfp_ver = NO_VER,

		.pm4_jt_idx = 0x8AD,

		.pm4_jt_idx = 0x8AD,

		.pm4_jt_addr = 0x2E4,

		.pm4_jt_addr = 0x2E4,

		.pfp_jt_idx = 0x201,

		.pfp_jt_idx = 0x201,
@@ -110,13 +69,12 @@ static const struct adreno_gpulist { 
		.major = 0,

		.major = 0,

		.minor = 5,

		.minor = 5,

		.patchid = 0x10,

		.patchid = 0x10,

		.pm4fw = "a330_pm4.fw",

		.pm4fw_name = "a330_pm4.fw",

		.pfpfw = "a330_pfp.fw",

		.pfpfw_name = "a330_pfp.fw",

		.features = ADRENO_USES_OCMEM | IOMMU_FLUSH_TLB_ON_MAP,

		.features = ADRENO_USES_OCMEM | IOMMU_FLUSH_TLB_ON_MAP |

			ADRENO_WARM_START,

		.gpudev = &adreno_a3xx_gpudev,

		.gpudev = &adreno_a3xx_gpudev,

		.gmem_size = SZ_128K,

		.gmem_size = SZ_128K,

		.sync_lock_pm4_ver = NO_VER,

		.sync_lock_pfp_ver = NO_VER,

		.pm4_jt_idx = 0x8AD,

		.pm4_jt_idx = 0x8AD,

		.pm4_jt_addr = 0x2E4,

		.pm4_jt_addr = 0x2E4,

		.pfp_jt_idx = 0x201,

		.pfp_jt_idx = 0x201,
@@ -129,13 +87,12 @@ static const struct adreno_gpulist { 
		.major = 0,

		.major = 0,

		.minor = 5,

		.minor = 5,

		.patchid = 0x12,

		.patchid = 0x12,

		.features = ADRENO_USES_OCMEM  | IOMMU_FLUSH_TLB_ON_MAP,

		.features = ADRENO_USES_OCMEM  | IOMMU_FLUSH_TLB_ON_MAP |

		.pm4fw = "a330_pm4.fw",

			ADRENO_WARM_START,

		.pfpfw = "a330_pfp.fw",

		.pm4fw_name = "a330_pm4.fw",

		.pfpfw_name = "a330_pfp.fw",

		.gpudev = &adreno_a3xx_gpudev,

		.gpudev = &adreno_a3xx_gpudev,

		.gmem_size = SZ_128K,

		.gmem_size = SZ_128K,

		.sync_lock_pm4_ver = NO_VER,

		.sync_lock_pfp_ver = NO_VER,

		.pm4_jt_idx = 0x8AD,

		.pm4_jt_idx = 0x8AD,

		.pm4_jt_addr = 0x2E4,

		.pm4_jt_addr = 0x2E4,

		.pfp_jt_idx = 0x201,

		.pfp_jt_idx = 0x201,
@@ -148,8 +105,9 @@ static const struct adreno_gpulist { 
		.major = 0,

		.major = 0,

		.minor = 5,

		.minor = 5,

		.patchid = 0x20,

		.patchid = 0x20,

		.pm4fw = "a300_pm4.fw",

		.features = ADRENO_HAS_IOMMU_SYNC_LOCK,

		.pfpfw = "a300_pfp.fw",

		.pm4fw_name = "a300_pm4.fw",

		.pfpfw_name = "a300_pfp.fw",

		.gpudev = &adreno_a3xx_gpudev,

		.gpudev = &adreno_a3xx_gpudev,

		.gmem_size = SZ_128K,

		.gmem_size = SZ_128K,

		.sync_lock_pm4_ver = 0x3FF037,

		.sync_lock_pm4_ver = 0x3FF037,
@@ -161,12 +119,10 @@ static const struct adreno_gpulist { 
		.major = 0,

		.major = 0,

		.minor = 6,

		.minor = 6,

		.patchid = 0x00,

		.patchid = 0x00,

		.pm4fw = "a300_pm4.fw",

		.pm4fw_name = "a300_pm4.fw",

		.pfpfw = "a300_pfp.fw",

		.pfpfw_name = "a300_pfp.fw",

		.gpudev = &adreno_a3xx_gpudev,

		.gpudev = &adreno_a3xx_gpudev,

		.gmem_size = SZ_128K,

		.gmem_size = SZ_128K,

		.sync_lock_pm4_ver = NO_VER,

		.sync_lock_pfp_ver = NO_VER,

	},

	},

	{

	{

		.gpurev = ADRENO_REV_A310,

		.gpurev = ADRENO_REV_A310,
@@ -174,13 +130,11 @@ static const struct adreno_gpulist { 
		.major = 1,

		.major = 1,

		.minor = 0,

		.minor = 0,

		.patchid = 0x10,

		.patchid = 0x10,

		.features = ADRENO_USES_OCMEM,

		.features = ADRENO_USES_OCMEM | ADRENO_WARM_START,

		.pm4fw = "a330_pm4.fw",

		.pm4fw_name = "a330_pm4.fw",

		.pfpfw = "a330_pfp.fw",

		.pfpfw_name = "a330_pfp.fw",

		.gpudev = &adreno_a3xx_gpudev,

		.gpudev = &adreno_a3xx_gpudev,

		.gmem_size = SZ_512K,

		.gmem_size = SZ_512K,

		.sync_lock_pm4_ver = NO_VER,

		.sync_lock_pfp_ver = NO_VER,

		.pm4_jt_idx = 0x8AD,

		.pm4_jt_idx = 0x8AD,

		.pm4_jt_addr = 0x2E4,

		.pm4_jt_addr = 0x2E4,

		.pfp_jt_idx = 0x201,

		.pfp_jt_idx = 0x201,
@@ -192,13 +146,12 @@ static const struct adreno_gpulist { 
		.major = 2,

		.major = 2,

		.minor = 0,

		.minor = 0,

		.patchid = ANY_ID,

		.patchid = ANY_ID,

		.features = ADRENO_USES_OCMEM  | IOMMU_FLUSH_TLB_ON_MAP,

		.features = ADRENO_USES_OCMEM  | IOMMU_FLUSH_TLB_ON_MAP |

		.pm4fw = "a420_pm4.fw",

			ADRENO_WARM_START | ADRENO_USE_BOOTSTRAP,

		.pfpfw = "a420_pfp.fw",

		.pm4fw_name = "a420_pm4.fw",

		.pfpfw_name = "a420_pfp.fw",

		.gpudev = &adreno_a4xx_gpudev,

		.gpudev = &adreno_a4xx_gpudev,

		.gmem_size = (SZ_1M + SZ_512K),

		.gmem_size = (SZ_1M + SZ_512K),

		.sync_lock_pm4_ver = NO_VER,

		.sync_lock_pfp_ver = NO_VER,

		.pm4_jt_idx = 0x901,

		.pm4_jt_idx = 0x901,

		.pm4_jt_addr = 0x300,

		.pm4_jt_addr = 0x300,

		.pfp_jt_idx = 0x401,

		.pfp_jt_idx = 0x401,

drivers/gpu/msm/adreno.c

+140 −157

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/msm/adreno.h

+138 −44

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/msm/adreno_a3xx.c

+65 −49

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/msm/adreno_a3xx_snapshot.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -473,10 +473,10 @@ void *a3xx_snapshot(struct adreno_device *adreno_dev, void *snapshot, 
	int *remain, int hang)

	int *remain, int hang)

{

{

	struct kgsl_device *device = &adreno_dev->dev;

	struct kgsl_device *device = &adreno_dev->dev;

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	struct kgsl_snapshot_registers_list list;

	struct kgsl_snapshot_registers_list list;

	struct kgsl_snapshot_registers regs[5];

	struct kgsl_snapshot_registers regs[5];

	struct adreno_snapshot_data *snap_data =

	struct adreno_snapshot_data *snap_data = gpudev->snapshot_data;

				adreno_dev->gpudev->snapshot_data;





	list.registers = regs;

	list.registers = regs;

	list.count = 0;

	list.count = 0;