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Commit 1f28db31 authored by Yan He's avatar Yan He
Browse files

msm: pcie: add the option for N_FTS 



Add the option to configure the number of fast training sequences
sent when the link state is changed from L0s to L0.

Change-Id: Ib6ff00e958fc5eb7d5ffbab05f377196b4384faa
CRs-fixed: 620857
Signed-off-by: default avatarYan He <yanhe@codeaurora.org>
parent 360013b1

Documentation/devicetree/bindings/pci/msm_pcie.txt

+3 −0
Original line number Diff line number Diff line
@@ -48,6 +48,8 @@ Optional Properties: 
  - qcom,l1ss-supported: L1 sub-states (L1ss) is supported.

  - qcom,aux-clk-sync: The AUX clock is synchronous to the Core clock to

    support L1ss.

  - qcom,n-fts: The number of fast training sequences sent when the link state

    is changed from L0s to L0.

  - qcom,msi-gicm-addr: MSI address for GICv2m.

  - qcom,msi-gicm-base: MSI IRQ base for GICv2m.

  - qcom,ext-ref-clk: The reference clock is external.
@@ -112,6 +114,7 @@ Example: 
						<0>, <0>, <0>, <0>;

		qcom,l1ss-supported;

		qcom,aux-clk-sync;

		qcom,n-fts = <0x50>;

		qcom,msi-gicm-addr = <0xf9040040>;

		qcom,msi-gicm-base = <0x160>;

		qcom,ext-ref-clk;

arch/arm/mach-msm/pcie.c

+23 −5
Original line number Diff line number Diff line
@@ -70,6 +70,7 @@ 
#define PCIE20_DEVICE_CONTROL2_STATUS2 0x98



#define PCIE20_ACK_F_ASPM_CTRL_REG     0x70C

#define PCIE20_ACK_N_FTS               0xff00



#define PCIE20_PLR_IATU_VIEWPORT       0x900

#define PCIE20_PLR_IATU_CTRL1          0x904
@@ -621,17 +622,23 @@ static void msm_pcie_config_controller(struct msm_pcie_dev_t *dev) 
		readl_relaxed(dev->dm_core + PCIE20_PLR_IATU_UTAR));

	PCIE_DBG("PCIE20_PLR_IATU_CTRL2:0x%x\n",

		readl_relaxed(dev->dm_core + PCIE20_PLR_IATU_CTRL2));

}



static void msm_pcie_config_l1ss(struct msm_pcie_dev_t *dev)

{

	/* configure N_FTS */

	PCIE_DBG("Original PCIE20_ACK_F_ASPM_CTRL_REG:0x%x\n",

		readl_relaxed(dev->dm_core + PCIE20_ACK_F_ASPM_CTRL_REG));

	msm_pcie_write_mask(dev->dm_core + PCIE20_ACK_F_ASPM_CTRL_REG, 0,

						BIT(15));

	if (!dev->n_fts)

		msm_pcie_write_mask(dev->dm_core + PCIE20_ACK_F_ASPM_CTRL_REG,

					0, BIT(15));

	else

		msm_pcie_write_mask(dev->dm_core + PCIE20_ACK_F_ASPM_CTRL_REG,

					PCIE20_ACK_N_FTS,

					dev->n_fts << 8);

	PCIE_DBG("Updated PCIE20_ACK_F_ASPM_CTRL_REG:0x%x\n",

		readl_relaxed(dev->dm_core + PCIE20_ACK_F_ASPM_CTRL_REG));

}



static void msm_pcie_config_l1ss(struct msm_pcie_dev_t *dev)

{

	/* Enable the AUX Clock and the Core Clk to be synchronous for L1SS*/

	if (!dev->aux_clk_sync)

		msm_pcie_write_mask(dev->parf +
@@ -1244,6 +1251,17 @@ static int msm_pcie_probe(struct platform_device *pdev) 
	PCIE_DBG("AUX clock is %s synchronous to Core clock.\n",

		msm_pcie_dev[rc_idx].aux_clk_sync ? "" : "not");



	msm_pcie_dev[rc_idx].n_fts = 0;

	ret = of_property_read_u32((&pdev->dev)->of_node,

				"qcom,n-fts",

				&msm_pcie_dev[rc_idx].n_fts);



	if (ret)

		PCIE_DBG("n-fts does not exist.\n");

	else

		PCIE_DBG("n-fts: 0x%x.\n",

				msm_pcie_dev[rc_idx].n_fts);



	msm_pcie_dev[rc_idx].ext_ref_clk =

		of_property_read_bool((&pdev->dev)->of_node,

				"qcom,ext-ref-clk");

arch/arm/mach-msm/pcie.h

+1 −0
Original line number Diff line number Diff line
@@ -174,6 +174,7 @@ struct msm_pcie_dev_t { 


	bool                         l1ss_supported;

	bool                         aux_clk_sync;

	uint32_t                     n_fts;

	bool                         ext_ref_clk;

	uint32_t                     ep_latency;