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Commit 1d9016fb authored by Venkat Gopalakrishnan's avatar Venkat Gopalakrishnan Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: adjust SDC1 clock frequencies for msm8992 



The clock plan has changed for SDC1. Update its dt entries
to reflect the new clock rates that are supported.

Change-Id: I87ae4656959791490ff3849d4b03edc899e4ea60
Signed-off-by: default avatarVenkat Gopalakrishnan <venkatg@codeaurora.org>
parent ce15b0ab

arch/arm/boot/dts/qcom/msm8992-cdp.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -200,7 +200,7 @@ 
	pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;

	pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;



	qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 192000000 384000000>;

	qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 172000000 344000000>;

	qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";

	qcom,nonremovable;

	status = "ok";

arch/arm/boot/dts/qcom/msm8992-mtp.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -156,7 +156,7 @@ 
	pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;



	qcom,nonremovable;

	qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 192000000 384000000>;

	qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 172000000 344000000>;

	qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";

	status = "ok";

};