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Commit 1ceca4e8 authored by Alok Chauhan's avatar Alok Chauhan
Browse files

ARM: dts: msm: Introduce bus topology for msmtellurium 



Introduce bus topology for msmtellurium. This is a representation
of the bus connections in the SOC and allows the bus driver
to setup bandwidth requests from clients for the paths desired.

Change-Id: I73e74df29b45f4d95be630c017117b8992c8003a
Signed-off-by: default avatarAlok Chauhan <alokc@codeaurora.org>
parent dc18f56b

arch/arm/boot/dts/qcom/msmtellurium-bus.dtsi

0 → 100644
+981 −0

File added.

Preview size limit exceeded, changes collapsed.

arch/arm/boot/dts/qcom/msmtellurium.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -107,6 +107,7 @@ 
#include "msmtellurium-ipcrouter.dtsi"

#include "msm-gdsc-8916.dtsi"

#include "msmtellurium-coresight.dtsi"

#include "msmtellurium-bus.dtsi"



&soc {

	#address-cells = <1>;

include/dt-bindings/msm/msm-bus-ids.h

+448 −315
Original line number Diff line number Diff line 
/* Copyright (c) 2014, The Linux Foundation. All rights reserved.

/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -28,6 +28,10 @@ 
#define	MSM_BUS_FAB_PERIPH_NOC 4096

#define	MSM_BUS_FAB_CONFIG_NOC 5120

#define	MSM_BUS_FAB_OCMEM_VNOC 6144

#define	MSM_BUS_FAB_MMSS_AHB 2049

#define	MSM_BUS_FAB_A0_NOC 6145

#define	MSM_BUS_FAB_A1_NOC 6146

#define	MSM_BUS_FAB_A2_NOC 6147



#define	MSM_BUS_MASTER_FIRST 1

#define	MSM_BUS_MASTER_AMPSS_M0 1
@@ -59,6 +63,7 @@ 
#define	MSM_BUS_MASTER_JPEG_DEC 27

#define	MSM_BUS_MASTER_GRAPHICS_2D_CORE0 28

#define	MSM_BUS_MASTER_VFE 29

#define	MSM_BUS_MASTER_VFE0 MSM_BUS_MASTER_VFE

#define	MSM_BUS_MASTER_VPE 30

#define	MSM_BUS_MASTER_JPEG_ENC 31

#define	MSM_BUS_MASTER_GRAPHICS_2D_CORE1 32
@@ -69,10 +74,10 @@ 
#define	MSM_BUS_MASTER_RPM 37

#define	MSM_BUS_MASTER_MSS 38

#define	MSM_BUS_MASTER_RIVA 39

#define	MSM_BUS_SYSTEM_MASTER_UNUSED_6 40

#define	MSM_BUS_MASTER_SNOC_VMEM 40

#define	MSM_BUS_MASTER_MSS_SW_PROC 41

#define	MSM_BUS_MASTER_MSS_FW_PROC 42

#define	MSM_BUS_MMSS_MASTER_UNUSED_2 43

#define	MSM_BUS_MASTER_HMSS 43

#define	MSM_BUS_MASTER_GSS_NAV 44

#define	MSM_BUS_MASTER_PCIE 45

#define	MSM_BUS_MASTER_SATA 46
@@ -137,7 +142,9 @@ 
#define	MSM_BUS_MASTER_TCU_1 105

#define	MSM_BUS_MASTER_CPP 106

#define	MSM_BUS_MASTER_AUDIO 107

#define	MSM_BUS_MASTER_LAST 108

#define	MSM_BUS_MASTER_PCIE_2 108

#define	MSM_BUS_MASTER_VFE1 109

#define	MSM_BUS_MASTER_LAST 110



#define MSM_BUS_SYSTEM_FPB_MASTER_SYSTEM MSM_BUS_SYSTEM_MASTER_SYSTEM_FPB

#define MSM_BUS_CPSS_FPB_MASTER_SYSTEM MSM_BUS_SYSTEM_MASTER_CPSS_FPB
@@ -197,7 +204,18 @@ 
#define	MSM_BUS_PNOC_INT_5 10052

#define	MSM_BUS_PNOC_INT_6 10053

#define	MSM_BUS_PNOC_INT_7 10054

#define	MSM_BUS_INT_LAST 10055

#define	MSM_BUS_BIMC_SNOC_1_MAS 10055

#define	MSM_BUS_BIMC_SNOC_1_SLV 10056

#define	MSM_BUS_PNOC_A1NOC_MAS 10057

#define	MSM_BUS_PNOC_A1NOC_SLV 10058

#define	MSM_BUS_CNOC_A1NOC_MAS 10059

#define	MSM_BUS_A0NOC_SNOC_MAS 10060

#define	MSM_BUS_A0NOC_SNOC_SLV 10061

#define	MSM_BUS_A1NOC_SNOC_SLV 10062

#define	MSM_BUS_A1NOC_SNOC_MAS 10063

#define	MSM_BUS_A2NOC_SNOC_MAS 10064

#define	MSM_BUS_A2NOC_SNOC_SLV 10065

#define	MSM_BUS_INT_LAST 10066



#define	MSM_BUS_INT_TEST_ID	20000

#define	MSM_BUS_INT_TEST_LAST	20050
@@ -368,7 +386,47 @@ 
#define	MSM_BUS_SLAVE_PCIE_PARF 674

#define	MSM_BUS_SLAVE_USB3_PHY_CFG 675

#define	MSM_BUS_SLAVE_IPA_CFG 676

#define	MSM_BUS_SLAVE_LAST 677

#define	MSM_BUS_SLAVE_A0NOC_SNOC 677

#define	MSM_BUS_SLAVE_A1NOC_SNOC 678

#define	MSM_BUS_SLAVE_A2NOC_SNOC 679

#define	MSM_BUS_SLAVE_HMSS_L3 680

#define	MSM_BUS_SLAVE_PIMEM_CFG 681

#define	MSM_BUS_SLAVE_DCC_CFG 682

#define	MSM_BUS_SLAVE_QDSS_RBCPR_APU_CFG 683

#define	MSM_BUS_SLAVE_PCIE_2_CFG 684

#define	MSM_BUS_SLAVE_PCIE20_AHB2PHY 685

#define	MSM_BUS_SLAVE_A0NOC_CFG 686

#define	MSM_BUS_SLAVE_A1NOC_CFG 687

#define	MSM_BUS_SLAVE_A2NOC_CFG 688

#define	MSM_BUS_SLAVE_A1NOC_MPU_CFG 689

#define	MSM_BUS_SLAVE_A2NOC_MPU_CFG 690

#define	MSM_BUS_SLAVE_A0NOC_SMMU_CFG 691

#define	MSM_BUS_SLAVE_A1NOC_SMMU_CFG 692

#define	MSM_BUS_SLAVE_A2NOC_SMMU_CFG 693

#define	MSM_BUS_SLAVE_LPASS_SMMU_CFG 694

#define	MSM_BUS_SLAVE_MMAGIC_CFG 695

#define	MSM_BUS_SLAVE_VENUS_THROTTLE_CFG 696

#define	MSM_BUS_SLAVE_SSC_CFG 697

#define	MSM_BUS_SLAVE_DSA_CFG 698

#define	MSM_BUS_SLAVE_DSA_MPU_CFG 699

#define	MSM_BUS_SLAVE_DISPLAY_THROTTLE_CFG 700

#define	MSM_BUS_SLAVE_SMMU_CPP_CFG 701

#define	MSM_BUS_SLAVE_SMMU_JPEG_CFG 702

#define	MSM_BUS_SLAVE_SMMU_MDP_CFG 703

#define	MSM_BUS_SLAVE_SMMU_ROTATOR_CFG 704

#define	MSM_BUS_SLAVE_SMMU_VENUS_CFG 705

#define	MSM_BUS_SLAVE_SMMU_VFE_CFG 706

#define	MSM_BUS_SLAVE_A0NOC_MPU_CFG 707

#define	MSM_BUS_SLAVE_VMEM_CFG 708

#define	MSM_BUS_SLAVE_CAMERA_THROTTLE_CFG 709

#define	MSM_BUS_SLAVE_VMEM 710

#define	MSM_BUS_SLAVE_AHB2PHY 711

#define	MSM_BUS_SLAVE_PIMEM 712

#define	MSM_BUS_SLAVE_SNOC_VMEM 713

#define	MSM_BUS_SLAVE_PCIE_2 714

#define	MSM_BUS_SLAVE_RBCPR_MX 715

#define	MSM_BUS_SLAVE_RBCPR_CX 716

#define	MSM_BUS_SLAVE_LAST 717



#define	MSM_BUS_SYSTEM_FPB_SLAVE_SYSTEM  MSM_BUS_SYSTEM_SLAVE_SYSTEM_FPB

#define MSM_BUS_CPSS_FPB_SLAVE_SYSTEM MSM_BUS_SYSTEM_SLAVE_CPSS_FPB
@@ -392,6 +450,7 @@ 
#define	ICBID_MASTER_VIDEO_P0 ICBID_MASTER_VIDEO

#define	ICBID_MASTER_VIDEO_P1 10

#define	ICBID_MASTER_VFE 11

#define	ICBID_MASTER_VFE0 ICBID_MASTER_VFE

#define	ICBID_MASTER_CNOC_ONOC_CFG 12

#define	ICBID_MASTER_JPEG_OCMEM 13

#define	ICBID_MASTER_MDP_OCMEM 14
@@ -402,6 +461,7 @@ 
#define	ICBID_MASTER_QDSS_BAM 19

#define	ICBID_MASTER_SNOC_CFG 20

#define	ICBID_MASTER_BIMC_SNOC 21

#define	ICBID_MASTER_BIMC_SNOC_0 ICBID_MASTER_BIMC_SNOC

#define	ICBID_MASTER_CNOC_SNOC 22

#define	ICBID_MASTER_CRYPTO 23

#define	ICBID_MASTER_CRYPTO_CORE0 ICBID_MASTER_CRYPTO
@@ -495,16 +555,37 @@ 
#define	ICBID_MASTER_BIMC_INT_1 105

#define	ICBID_MASTER_CAMERA 106

#define	ICBID_MASTER_RICA 107

#define ICBID_MASTER_PCNOC_S_5	129

#define	ICBID_MASTER_SNOC_BIMC_2 108

#define	ICBID_MASTER_BIMC_SNOC_1 109

#define	ICBID_MASTER_A0NOC_SNOC 110

#define	ICBID_MASTER_A1NOC_SNOC 111

#define	ICBID_MASTER_A2NOC_SNOC 112

#define	ICBID_MASTER_PIMEM 113

#define	ICBID_MASTER_SNOC_VMEM 114

#define	ICBID_MASTER_CPP 115

#define	ICBID_MASTER_CNOC_A1NOC 116

#define	ICBID_MASTER_PNOC_A1NOC 117

#define	ICBID_MASTER_HMSS 118

#define	ICBID_MASTER_PCIE_2 119

#define	ICBID_MASTER_ROTATOR 120

#define	ICBID_MASTER_VENUS_VMEM 121

#define	ICBID_MASTER_DCC 122

#define	ICBID_MASTER_MCDMA 123

#define	ICBID_MASTER_PCNOC_INT_2 124

#define	ICBID_MASTER_PCNOC_INT_3 125

#define	ICBID_MASTER_PCNOC_INT_4 126

#define	ICBID_MASTER_PCNOC_INT_5 127

#define	ICBID_MASTER_PCNOC_INT_6 128

#define	ICBID_MASTER_PCNOC_S_5 129

#define	ICBID_MASTER_SENSORS_AHB 130

#define	ICBID_MASTER_SENSORS_PROC 131

#define	ICBID_MASTER_QSPI 132

#define	ICBID_MASTER_VFE1 133



#define	ICBID_SLAVE_EBI1 0

#define	ICBID_SLAVE_APPSS_L2 1

#define	ICBID_SLAVE_BIMC_SNOC 2

#define	ICBID_SLAVE_BIMC_SNOC_0 ICBID_SLAVE_BIMC_SNOC

#define	ICBID_SLAVE_CAMERA_CFG 3

#define	ICBID_SLAVE_DISPLAY_CFG 4

#define	ICBID_SLAVE_OCMEM_CFG 5
@@ -649,13 +730,65 @@ 
#define	ICBID_SLAVE_BIMC_INT_0 134

#define	ICBID_SLAVE_BIMC_INT_1 135

#define	ICBID_SLAVE_RICA_CFG 136

#define ICBID_SLAVE_PCNOC_S_5	189

#define	ICBID_SLAVE_SNOC_BIMC_2 137

#define	ICBID_SLAVE_BIMC_SNOC_1 138

#define	ICBID_SLAVE_PNOC_A1NOC 139

#define	ICBID_SLAVE_SNOC_VMEM 140

#define	ICBID_SLAVE_A0NOC_SNOC 141

#define	ICBID_SLAVE_A1NOC_SNOC 142

#define	ICBID_SLAVE_A2NOC_SNOC 143

#define	ICBID_SLAVE_A0NOC_CFG 144

#define	ICBID_SLAVE_A0NOC_MPU_CFG 145

#define	ICBID_SLAVE_A0NOC_SMMU_CFG 146

#define	ICBID_SLAVE_A1NOC_CFG 147

#define	ICBID_SLAVE_A1NOC_MPU_CFG 148

#define	ICBID_SLAVE_A1NOC_SMMU_CFG 149

#define	ICBID_SLAVE_A2NOC_CFG 150

#define	ICBID_SLAVE_A2NOC_MPU_CFG 151

#define	ICBID_SLAVE_A2NOC_SMMU_CFG 152

#define	ICBID_SLAVE_AHB2PHY 153

#define	ICBID_SLAVE_CAMERA_THROTTLE_CFG 154

#define	ICBID_SLAVE_DCC_CFG 155

#define	ICBID_SLAVE_DISPLAY_THROTTLE_CFG 156

#define	ICBID_SLAVE_DSA_CFG 157

#define	ICBID_SLAVE_DSA_MPU_CFG 158

#define	ICBID_SLAVE_SSC_MPU_CFG 159

#define	ICBID_SLAVE_HMSS_L3 160

#define	ICBID_SLAVE_LPASS_SMMU_CFG 161

#define	ICBID_SLAVE_MMAGIC_CFG 162

#define	ICBID_SLAVE_PCIE20_AHB2PHY 163

#define	ICBID_SLAVE_PCIE_2 164

#define	ICBID_SLAVE_PCIE_2_CFG 165

#define	ICBID_SLAVE_PIMEM 166

#define	ICBID_SLAVE_PIMEM_CFG 167

#define	ICBID_SLAVE_QDSS_RBCPR_APU_CFG 168

#define	ICBID_SLAVE_RBCPR_CX 169

#define	ICBID_SLAVE_RBCPR_MX 170

#define	ICBID_SLAVE_SMMU_CPP_CFG 171

#define	ICBID_SLAVE_SMMU_JPEG_CFG 172

#define	ICBID_SLAVE_SMMU_MDP_CFG 173

#define	ICBID_SLAVE_SMMU_ROTATOR_CFG 174

#define	ICBID_SLAVE_SMMU_VENUS_CFG 175

#define	ICBID_SLAVE_SMMU_VFE_CFG 176

#define	ICBID_SLAVE_SSC_CFG 177

#define	ICBID_SLAVE_VENUS_THROTTLE_CFG 178

#define	ICBID_SLAVE_VMEM 179

#define	ICBID_SLAVE_VMEM_CFG 180

#define	ICBID_SLAVE_QDSS_MPU_CFG 181

#define	ICBID_SLAVE_USB3_PHY_CFG 182

#define	ICBID_SLAVE_IPA_CFG 183

#define	ICBID_SLAVE_PCNOC_INT_2 184

#define	ICBID_SLAVE_PCNOC_INT_3 185

#define	ICBID_SLAVE_PCNOC_INT_4 186

#define	ICBID_SLAVE_PCNOC_INT_5 187

#define	ICBID_SLAVE_PCNOC_INT_6 188

#define ICBID_SLAVE_USB3_PHY_CFG 182

#define ICBID_SLAVE_IPA_CFG 183

#define	ICBID_SLAVE_PCNOC_S_5 189

#define	ICBID_SLAVE_QSPI 190

#define	ICBID_SLAVE_A1NOC_MS_MPU_CFG 191

#define	ICBID_SLAVE_A2NOC_MS_MPU_CFG 192

#define	ICBID_SLAVE_MODEM_Q6_SMMU_CFG 193

#define	ICBID_SLAVE_MSS_MPU_CFG 194

#define	ICBID_SLAVE_MSS_PROC_MS_MPU_CFG 195

#define	ICBID_SLAVE_SKL 196



#endif