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Commit 1a3e51df authored by Vivek Veenam's avatar Vivek Veenam
Browse files

Arm: dts: msm: camera: Enable csiphy_clk in CSIPHY init 



csiphy_clk is enabled and disabled as part of csid
init and release. In release sequence csid release
is called before csiphy release and csiphy_clk is
disabled in csid release. This causes unclock register
access in csiphy release.
Enable and disable csiphy_clk in csiphy init and release.

CRs-Fixed: 640406
Change-Id: I04505e71e82e6766da09c2a98cfa4be7e8afea5a
Signed-off-by: default avatarVivek Veenam <vveenam@codeaurora.org>
parent 93980fdb

arch/arm/boot/dts/qcom/msm8916-camera.dtsi

+24 −24
Original line number Diff line number Diff line
@@ -28,14 +28,15 @@ 
			<&clock_gcc clk_gcc_camss_ispif_ahb_clk>,

			<&clock_gcc clk_csi0phytimer_clk_src>,

			<&clock_gcc clk_gcc_camss_csi0phytimer_clk>,

			<&clock_gcc clk_camss_ahb_clk_src>;

			<&clock_gcc clk_camss_ahb_clk_src>,

			<&clock_gcc clk_gcc_camss_csi0phy_clk>;

		clock-names = "camss_top_ahb_clk", "ispif_ahb_clk",

			"csiphy_timer_src_clk", "csiphy_timer_clk",

			"camss_ahb_clk";

			"camss_ahb_clk", "csi_phy_clk";

		qcom,clock-names = "camss_top_ahb_clk", "ispif_ahb_clk",

			"csiphy_timer_src_clk", "csiphy_timer_clk",

			"camss_ahb_clk";

		qcom,clock-rates = <0 0 200000000 0 0>;

			"camss_ahb_clk", "csi_phy_clk";

		qcom,clock-rates = <0 0 200000000 0 0 0>;

	};



	qcom,csiphy@1b0b000 {
@@ -50,14 +51,15 @@ 
			<&clock_gcc clk_gcc_camss_ispif_ahb_clk>,

			<&clock_gcc clk_csi1phytimer_clk_src>,

			<&clock_gcc clk_gcc_camss_csi1phytimer_clk>,

			<&clock_gcc clk_camss_ahb_clk_src>;

			<&clock_gcc clk_camss_ahb_clk_src>,

			<&clock_gcc clk_gcc_camss_csi1phy_clk>;

		clock-names = "camss_top_ahb_clk", "ispif_ahb_clk",

			"csiphy_timer_src_clk", "csiphy_timer_clk",

			"camss_ahb_clk";

			"camss_ahb_clk",  "csi_phy_clk";

		qcom,clock-names = "camss_top_ahb_clk", "ispif_ahb_clk",

			"csiphy_timer_src_clk", "csiphy_timer_clk",

			"camss_ahb_clk";

		qcom,clock-rates = <0 0 200000000 0 0>;

			"camss_ahb_clk",  "csi_phy_clk";

		qcom,clock-rates = <0 0 200000000 0 0 0>;

	};



	qcom,csid@1b08000  {
@@ -74,19 +76,18 @@ 
			<&clock_gcc clk_gcc_camss_csi0_ahb_clk>,

			<&clock_gcc clk_csi0_clk_src>,

			<&clock_gcc clk_gcc_camss_csi0_clk>,

			 <&clock_gcc clk_gcc_camss_csi0phy_clk>,

			<&clock_gcc clk_gcc_camss_csi0pix_clk>,

			<&clock_gcc clk_gcc_camss_csi0rdi_clk>,

			<&clock_gcc clk_gcc_camss_ahb_clk>;

		clock-names = "camss_top_ahb_clk",

			"ispif_ahb_clk", "csi_ahb_clk", "csi_src_clk",

			"csi_clk", "csi_phy_clk", "csi_pix_clk",

			"csi_clk",  "csi_pix_clk",

			"csi_rdi_clk", "camss_ahb_clk";

		qcom,clock-names = "camss_top_ahb_clk",

			"ispif_ahb_clk", "csi_ahb_clk", "csi_src_clk",

			"csi_clk", "csi_phy_clk", "csi_pix_clk",

			"csi_clk", "csi_pix_clk",

			"csi_rdi_clk", "camss_ahb_clk";

		qcom,clock-rates = <0 0 0 200000000 0 0 0 0 0>;

		qcom,clock-rates = <0 0 0 200000000 0 0 0 0>;

     };



	qcom,csid@1b08400 {
@@ -103,19 +104,18 @@ 
			<&clock_gcc clk_gcc_camss_csi1_ahb_clk>,

			<&clock_gcc clk_csi1_clk_src>,

			<&clock_gcc clk_gcc_camss_csi1_clk>,

			<&clock_gcc clk_gcc_camss_csi1phy_clk>,

			<&clock_gcc clk_gcc_camss_csi1pix_clk>,

			<&clock_gcc clk_gcc_camss_csi1rdi_clk>,

			<&clock_gcc clk_gcc_camss_ahb_clk>;

		clock-names = "camss_top_ahb_clk",

			"ispif_ahb_clk", "csi_ahb_clk", "csi_src_clk",

			"csi_clk", "csi_phy_clk", "csi_pix_clk",

			"csi_clk", "csi_pix_clk",

			"csi_rdi_clk", "camss_ahb_clk";

		qcom,clock-names = "camss_top_ahb_clk",

			"ispif_ahb_clk", "csi_ahb_clk", "csi_src_clk",

			"csi_clk", "csi_phy_clk", "csi_pix_clk",

			"csi_clk", "csi_pix_clk",

			"csi_rdi_clk", "camss_ahb_clk";

		qcom,clock-rates = <0 0 0 200000000 0 0 0 0 0>;

		qcom,clock-rates = <0 0 0 200000000 0 0 0 0>;



	};