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Commit 1a3e51df authored by Vivek Veenam's avatar Vivek Veenam
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Arm: dts: msm: camera: Enable csiphy_clk in CSIPHY init



csiphy_clk is enabled and disabled as part of csid
init and release. In release sequence csid release
is called before csiphy release and csiphy_clk is
disabled in csid release. This causes unclock register
access in csiphy release.
Enable and disable csiphy_clk in csiphy init and release.

CRs-Fixed: 640406
Change-Id: I04505e71e82e6766da09c2a98cfa4be7e8afea5a
Signed-off-by: default avatarVivek Veenam <vveenam@codeaurora.org>
parent 93980fdb
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