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Commit 196149e1 authored by Kiran Gunda's avatar Kiran Gunda
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ARM: dts: msm: Configure SPI node for tellurium



Configure the BLSP1QUP0 in SPI mode.

Change-Id: Ibd72b148cf34304c95ed818cbf74ca0b5650f542
Signed-off-by: default avatarKiran Gunda <kgunda@codeaurora.org>
parent 18c43109
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+52 −1
Original line number Diff line number Diff line
/*
 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
@@ -156,5 +156,56 @@
				drive-strength = <2>; /* 2 MA */
			};
		};

		spi0_active {
			/* MOSI, MISO, CLK */
			qcom,pins = <&gp 0>, <&gp 1>, <&gp 3>;
			qcom,num-grp-pins = <3>;
			qcom,pin-func = <1>;
			label = "spi0-active";
			/* active state */
			spi0_default: spi0_default {
				drive-strength = <12>; /* 12 MA */
				bias-disable = <0>; /* No PULL */
			};
		};

		spi0_suspend {
			/* MOSI, MISO, CLK */
			qcom,pins = <&gp 0>, <&gp 1>, <&gp 3>;
			qcom,num-grp-pins = <3>;
			qcom,pin-func = <0>;
			label = "spi0-suspend";
			/* suspended state */
			spi0_sleep: spi0_sleep {
				drive-strength = <2>; /* 2 MA */
				bias-pull-down; /* PULL Down */
			};
		};

		spi0_cs0_active {
			/* CS */
			qcom,pins = <&gp 2>;
			qcom,num-grp-pins = <1>;
			qcom,pin-func = <1>;
			label = "spi0-cs0-active";
			spi0_cs0_active: cs0_active {
				drive-strength = <2>;
				bias-disable = <0>;
			};
		};

		spi0_cs0_suspend {
			/* CS */
			qcom,pins = <&gp 2>;
			qcom,num-grp-pins = <1>;
			qcom,pin-func = <0>;
			label = "spi0-cs0-suspend";
			spi0_cs0_sleep: cs0_sleep {
				drive-strength = <2>;
				bias-disable = <0>;
			};
		};

	};
};
+26 −0
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@
	aliases {
		sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
		sdhc2 = &sdhc_2; /* SDC2 SD card slot */
		spi0 = &spi_0;
	};

	memory {
@@ -686,6 +687,31 @@
		qcom,firmware-name = "venus";
		linux,contiguous-region = <&venus_mem>;
	};

	spi_0: spi@78B5000 { /* BLSP1 QUP0 */
		compatible = "qcom,spi-qup-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "spi_physical", "spi_bam_physical";
		reg = <0x78B5000 0x600>,
		      <0x7884000 0x23000>;
		interrupt-names = "spi_irq", "spi_bam_irq";
		interrupts = <0 95 0>, <0 238 0>;
		spi-max-frequency = <19200000>;
		pinctrl-names = "spi_default", "spi_sleep";
		pinctrl-0 = <&spi0_default &spi0_cs0_active>;
		pinctrl-1 = <&spi0_sleep &spi0_cs0_sleep>;
		clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
			 <&clock_gcc clk_gcc_blsp1_qup1_spi_apps_clk>;
		clock-names = "iface_clk", "core_clk";
		qcom,infinite-mode = <0>;
		qcom,use-bam;
		qcom,use-pinctrl;
		qcom,ver-reg-exists;
		qcom,bam-consumer-pipe-index = <4>;
		qcom,bam-producer-pipe-index = <5>;
		qcom,master-id = <86>;
	};
};

&gdsc_venus {