Merge "arm64: implement flush_cache_louis() for ARM64" (1730231f) · Commits · e / devices / android_kernel_sony_msm8994

arch/arm64/include/asm/cacheflush.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -3,6 +3,7 @@
		*
		* Copyright (C) 1999-2002 Russell King.
		* Copyright (C) 2012 ARM Ltd.
		* Copyright (c) 2014, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 as
		@@ -70,6 +71,7 @@
		* - size - region size
		*/
		extern void flush_cache_all(void);
		extern void flush_cache_louis(void);
		extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
		extern void flush_icache_range(unsigned long start, unsigned long end);
		extern void __flush_dcache_area(void *addr, size_t len);

+34 −0

Original line number	Diff line number	Diff line
		@@ -3,6 +3,7 @@
		*
		* Copyright (C) 2001 Deep Blue Solutions Ltd.
		* Copyright (C) 2012 ARM Ltd.
		* Copyright (c) 2014, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 as
		@@ -23,6 +24,39 @@

		#include "proc-macros.S"

		/*
		* flush_dcache_louis()
		*
		* Flush the D-cache up to the Level of Unification Inner Shareable
		*
		* Corrupted registers: x0-x7, x9-x11
		*/

		ENTRY(flush_dcache_louis)
		dsb sy // ensure ordering with previous memory accesses
		mrs x0, clidr_el1 // read clidr
		and x3, x0, #(7 << 21) // extract LoUIS from clidr
		lsr x3, x3, #20 // x3 = LoUIS * 2
		cbz x3, done // if LoUIS is 0, then no need to clean
		mov x10, #0 // start clean at cache level 0
		b loop1 // start flushing cache levels
		done:
		ret
		ENDPROC(flush_dcache_louis)

		/*
		* flush_kern_cache_louis(void)
		*
		* Flush the data cache up to Level of Unification Inner Shareable.
		* Invalidate the I-cache to the point of unification.
		*/
		ENTRY(flush_cache_louis)
		bl flush_dcache_louis
		mov x0, #0
		ic ialluis // I+BTB cache invalidate
		ret
		ENDPROC(flush_cache_louis)

		/*
		* __flush_dcache_all()
		*